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74AC377SCX PDF预览

74AC377SCX

更新时间: 2024-09-08 00:00:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器时钟
页数 文件大小 规格书
10页 120K
描述
Octal D-Type Flip-Flop with Clock Enable

74AC377SCX 数据手册

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November 1988  
Revised March 2005  
74AC377 74ACT377  
Octal D-Type Flip-Flop with Clock Enable  
General Description  
Features  
The AC/ACT377 has eight edge-triggered, D-type flip-flops  
with individual D inputs and Q outputs. The common buff-  
ered Clock (CP) input loads all flip-flops simultaneously,  
when the Clock Enable (CE) is LOW.  
ICC reduced by 50%  
Ideal for addressable register applications  
Clock enable for address and data synchronization  
applications  
The register is fully edge-triggered. The state of each D  
input, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
The CE input must be stable only one setup time prior to  
the LOW-to-HIGH clock transition for predictable operation.  
Eight edge-triggered D-type flip-flops  
Buffered common clock  
Outputs source/sink 24 mA  
See 273 for master reset version  
See 373 for transparent latch version  
See 374 for 3-STATE version  
ACT377 has TTL-compatible inputs  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74AC377SC  
74AC377SJ  
74AC377MTC  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
MTC20  
MTC20  
74AC377MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74AC377PC  
N20A  
M20B  
M20D  
MTC20  
N20A  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
74ACT377SC  
74ACT377SJ  
74ACT377MTC  
74ACT377PC  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Note 1: _NLindicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
D0D7  
CE  
Data Inputs  
Clock Enable (Active LOW)  
Data Outputs  
Q0Q7  
CP  
Clock Pulse Input  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 2005 Fairchild Semiconductor Corporation  
DS009961  
www.fairchildsemi.com  

74AC377SCX 替代型号

型号 品牌 替代类型 描述 数据表
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