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74AC161MTR PDF预览

74AC161MTR

更新时间: 2024-11-10 23:23:59
品牌 Logo 应用领域
其他 - ETC 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 112K
描述
Synchronous Up Counter

74AC161MTR 数据手册

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74AC161  
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER  
HIGH SPEED:  
= 125MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 8µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
50TRANSMISSION LINE DRIVING  
CAPABILITY  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
TUBE  
t
t
PLH  
PHL  
DIP  
SOP  
74AC161B  
74AC161M  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
74AC161MTR  
74AC161TTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 161  
IMPROVED LATCH-UP IMMUNITY  
counting and parallel loading and sets all outputs  
on LOW state. A LOW signal on LOAD overrides  
counting and allows information on Parallel Data  
inputs to be loaded into the flip-flop on the next  
rising edge of CLOCK. With LOAD and CLEAR  
HIGH, PE and TE permit counting when both are  
HIGH. Conversely, a LOW signal on either PE and  
TE inhibits counting.  
The CARRY OUTPUT is HIGH when TE is HIGH  
and counter is in state 15.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74AC161 is an advanced high-speed CMOS  
SYNCRONOUS PRESETTABLE COUNTER  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS tecnology. It is a  
4 bit binary counter with Asynchronous Clear.  
The circuit have four fundamental modes of  
operation, in order of preference: synchronous  
reset, parallel load, count-up and hold. Four  
control inputs, (CLEAR), (LOAD), (PE) and (TE),  
determine the mode of operation as shown in the  
Truth Table. A LOW signal on CLEAR overrides  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/13  

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