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74ABT841PW,112 PDF预览

74ABT841PW,112

更新时间: 2024-09-17 15:31:11
品牌 Logo 应用领域
恩智浦 - NXP 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
15页 143K
描述
74ABT841 - 10-bit bus interface latch; 3-state TSSOP2 24-Pin

74ABT841PW,112 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP2包装说明:TSSOP, TSSOP24,.25
针数:24Reach Compliance Code:unknown
风险等级:5.58其他特性:POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION; WITH POWER-UP RESET
系列:ABTJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:7.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:10功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):38 mA
Prop。Delay @ Nom-Sup:6.2 ns传播延迟(tpd):6.7 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

74ABT841PW,112 数据手册

 浏览型号74ABT841PW,112的Datasheet PDF文件第2页浏览型号74ABT841PW,112的Datasheet PDF文件第3页浏览型号74ABT841PW,112的Datasheet PDF文件第4页浏览型号74ABT841PW,112的Datasheet PDF文件第5页浏览型号74ABT841PW,112的Datasheet PDF文件第6页浏览型号74ABT841PW,112的Datasheet PDF文件第7页 
74ABT841  
10-bit bus interface latch; 3-state  
Rev. 4 — 7 November 2011  
Product data sheet  
1. General description  
The 74ABT841 high performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT841 bus interface register is designed to provide extra data width for wider  
data/address paths of buses carrying parity.  
The 74ABT841 consists of ten D-type latches with 3-state outputs. The flip-flops appear  
transparent to the data when latch enable (LE) is HIGH. This allows asynchronous  
operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW  
transition, the data that meets the set-up and hold time is latched.  
Data appears on the bus when the output enable (OE) is LOW. When OE is HIGH the  
output is in the high-impedance state.  
2. Features and benefits  
High speed parallel latches  
Extra data width for wide address/data paths or buses carrying parity  
Ideal where high speed, light loading, or increased fan-in are required with MOS  
microprocessors  
Broadside pinout  
Output capability: +64 mA and 32 mA  
Power-up 3-state  
Power-up reset  
Latch-up protection exceeds 500 mA per JESD78B class II level A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
 
 

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