Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
FEATURES
• High speed parallel latches
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
• Extra data width for wide address/data paths or buses carrying
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
parity
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Slim DIP 300 mil package
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
• Broadside pinout
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up 3-State
• Power-up reset
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
PLH
PHL
C = 50pF; V = 5V
4.1
4
ns
pF
pF
nA
L
CC
C
Input capacitance
V = 0V or V
I CC
IN
Outputs disabled;
= 0V or V
C
Output capacitance
Total supply current
7
OUT
CCZ
V
O
CC
I
Outputs disabled; V = 5.5V
500
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT841 N
DWG NUMBER
SOT222-1
24-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT841 N
74ABT841 D
74ABT841 DB
74ABT841 PW
24-Pin plastic SO
74ABT841 D
SOT137-1
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
74ABT841 DB
74ABT841PW DH
SOT340-1
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
24
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
V
CC
Output enable input
(active-Low)
1
OE
23 Q0
22 Q1
21 Q2
20 Q3
19 Q4
18 Q5
17 Q6
16 Q7
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
D0-D9
Q0-Q9
Data inputs
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
Data outputs
TOP VIEW
Latch enable input (active
falling edge)
13
LE
12
24
GND
Ground (0V)
V
CC
Positive supply voltage
D8 10
D9 11
15
14
13
Q8
Q9
LE
GND 12
SA00247
1
1995 Sep 06
853-1628 15703