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74ABT845PWDH-T PDF预览

74ABT845PWDH-T

更新时间: 2024-09-17 13:04:51
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恩智浦 - NXP /
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74ABT845PWDH-T 数据手册

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Philips Semiconductors  
Product specification  
8-bit bus interface latch with set and reset  
(3-State)  
74ABT845  
FEATURES  
High speed parallel latches  
DESCRIPTION  
The 74ABT845 consists of eight D-type latches with 3-State outputs.  
In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two  
additional OE pins, making a total of three Output Enable (OE0,  
OE1, OE2) pins. The multiple Output enables allow multiuser control  
of the interface, e.g., CS, DMA, and RD/WR.  
Ideal where high speed, light loading, or increased fan-in are  
required with MOS microprocessors  
Broadside pinout  
Output capability: +64mA/–32mA  
Power-up 3-State  
Power-up reset  
Latch-up protection exceeds 500mA per Jedec Std 17  
ESD protection exceeds 2000 V per MIL STD 883 Method 3015  
and 200 V per Machine Model  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
Dn to Qn  
PLH  
PHL  
C = 50pF; V = 5V  
5.4  
4
ns  
pF  
pF  
nA  
L
CC  
C
Input capacitance  
V = 0V or V  
I CC  
IN  
Outputs disabled;  
= 0V or V  
C
Output capacitance  
Total supply current  
7
OUT  
CCZ  
V
O
CC  
I
Outputs disabled; V = 5.5V  
500  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE OUTSIDE NORTH AMERICA  
NORTH AMERICA  
74ABT845 N  
DWG NUMBER  
SOT222-1  
24-Pin Plastic DIP  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
74ABT845 N  
74ABT845 D  
74ABT845 DB  
74ABT845 PW  
24-Pin plastic SO  
74ABT845 D  
SOT137-1  
24-Pin Plastic SSOP Type II  
24-Pin Plastic TSSOP Type I  
74ABT845 DB  
74ABT845PW DH  
SOT340-1  
SOT355-1  
PIN CONFIGURATION  
PIN DESCRIPTION  
PIN NUMBER  
SYMBOL  
FUNCTION  
Output enable inputs  
(active-Low)  
1, 2, 23  
OE0 – OE2  
D0-D7  
24  
OE0  
OE1  
D0  
1
2
3
4
5
6
7
8
9
V
CC  
23 OE2  
22 Q0  
21 Q1  
20 Q2  
19 Q3  
18 Q4  
17 Q5  
16 Q6  
3, 4, 5, 6,  
7, 8, 9, 10  
Data inputs  
D1  
22, 21, 20, 19,18,  
17, 16, 15  
Q0-Q7  
MR  
Data outputs  
D2  
11  
13  
Master reset input (active-Low)  
D3  
Latch enable input  
(active-High)  
D4  
LE  
D5  
14  
12  
24  
PRE  
GND  
Preset input (active-Low)  
Ground (0V)  
D6  
D7 10  
MR 11  
15  
14  
13  
Q7  
V
CC  
Positive supply voltage  
PRE  
LE  
GND 12  
TOP VIEW  
SA00258  
1
1995 Sep 06  
853-1703 15702  

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