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74ABT162841DLRG4 PDF预览

74ABT162841DLRG4

更新时间: 2024-02-01 08:57:22
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
12页 356K
描述
ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, SSOP-56

74ABT162841DLRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP56,.4针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.61系列:ABT
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:18.415 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A湿度敏感等级:1
位数:10功能数量:2
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE WITH SERIES RESISTOR输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP56,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):89 mAProp。Delay @ Nom-Sup:6 ns
传播延迟(tpd):5.8 ns认证状态:Not Qualified
座面最大高度:2.79 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.49 mm
Base Number Matches:1

74ABT162841DLRG4 数据手册

 浏览型号74ABT162841DLRG4的Datasheet PDF文件第1页浏览型号74ABT162841DLRG4的Datasheet PDF文件第3页浏览型号74ABT162841DLRG4的Datasheet PDF文件第4页浏览型号74ABT162841DLRG4的Datasheet PDF文件第5页浏览型号74ABT162841DLRG4的Datasheet PDF文件第6页浏览型号74ABT162841DLRG4的Datasheet PDF文件第7页 
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢃꢇ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢃꢇ  
ꢉꢍ ꢎꢅꢏ ꢆ ꢅ ꢐ ꢀꢎꢏ ꢁꢆ ꢑ ꢒꢓꢄꢔ ꢑ ꢕꢎꢆ ꢖꢗ ꢑ ꢘꢄꢆꢔ ꢙ ꢑꢀ  
ꢚꢏ ꢆ ꢙ ꢛ ꢎꢀꢆꢄꢆ ꢑ ꢜꢐꢆ ꢗ ꢐꢆꢀ  
SCBS665C − JUNE 1996 − REVISED JUNE 2004  
description/ordering information (continued)  
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch  
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines significantly.  
The outputs, which are designed to sink up to 12 mA, include equivalent 25-series resistors to reduce  
overshoot and undershoot.  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
To ensure the high-impedance state during power up or power down, OE shall be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
FUNCTION TABLE  
(each 10-bit latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74ABT162841DLRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT162841DLG4 TI

功能相似

ABT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, SSOP-56
SN74ABT162841DLR TI

类似代替

20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT162841DL TI

类似代替

20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

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