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74ABT16373CSSCX_NL PDF预览

74ABT16373CSSCX_NL

更新时间: 2024-01-25 15:19:46
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
6页 87K
描述
Bus Driver, ABT Series, 2-Func, 8-Bit, True Output, BICMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48

74ABT16373CSSCX_NL 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:unknown风险等级:5.66
系列:ABTJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.875 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH传播延迟(tpd):5.5 ns
认证状态:Not Qualified座面最大高度:2.74 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:7.5 mmBase Number Matches:1

74ABT16373CSSCX_NL 数据手册

 浏览型号74ABT16373CSSCX_NL的Datasheet PDF文件第2页浏览型号74ABT16373CSSCX_NL的Datasheet PDF文件第3页浏览型号74ABT16373CSSCX_NL的Datasheet PDF文件第4页浏览型号74ABT16373CSSCX_NL的Datasheet PDF文件第5页浏览型号74ABT16373CSSCX_NL的Datasheet PDF文件第6页 
March 1994  
Revised May 2005  
74ABT16373  
16-Bit Transparent D-Type Latch with 3-STATE Outputs  
General Description  
Features  
The ABT16373 contains sixteen non-inverting latches with  
3-STATE outputs and is intended for bus oriented applica-  
tions. The device is byte controlled. The flip-flops appear  
transparent to the data when the Latch Enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup time  
is latched. Data appears on the bus when the Output  
Enable (OE) is LOW. When OE is HIGH, the outputs are in  
high Z state.  
Separate control logic for each byte  
16-bit version of the ABT373  
High impedance glitch free bus loading during entire  
power up and power down cycle  
Non-destructive hot insertion capability  
Guaranteed latch-up protection  
Ordering Code:  
Order Number  
74ABT16373CSSC  
74ABT16373CMTD  
Package Number  
MS48A  
Package Description  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Input (Active LOW)  
Latch Enable Input  
Data Inputs  
LEn  
D0D15  
O0O15  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS011666  
www.fairchildsemi.com  

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