74ABT16500

更新时间： 2024-11-25 22:45:55

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
9页	76K
描述
18-Bit Universal Bus Transceivers with 3-STATE Outputs

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数据手册

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74ABT16500 数据手册

April 1993

Revised January 1999

74ABT16500

18-Bit Universal Bus Transceivers with 3-STATE Outputs

plementary (OEAB is active HIGH and OEBA is active

LOW).

General Description

To ensure the high-impedance state during power up or

power down, OE should be tied to GND through a pulldown

resistor; the minimum value of the resistor is determined by

the current-sourcing capability of the driver.

The ABT16500 18-bit universal bus transceiver combines

D-type latches and D-type flip-flops to allow data flow in

transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the

device operates in the transparent mode when LEAB is

HIGH. When LEAB is LOW, the A data is latched if CLKAB

is held at a HIGH or LOW logic level. If LEAB is LOW, the A

bus data is stored in the latch/flip-flop on the HIGH-to-LOW

transition of CLKAB. Output-enable OEAB is active-high.

When OEAB is HIGH, the outputs are active. When OEAB

is LOW, the outputs are in the high-impedance state.

Features

■ Combines D-Type latches and D-Type flip-flops for

operation in transparent, latched, or clocked mode

■ Flow-through architecture optimizes PCB layout

■ Guaranteed latch-up protection

■ High impedance glitch free bus loading during entire

power up and power down cycle

■ Non-destructive hot insertion capability

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, and CLKBA. The output enables are com-

Ordering Code:

Order Number

74ABT16500CSSC

74ABT16500CMTD

Package Number

MS56A

Package Description

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

MTD56

Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.

Connection Diagram

Function Table (Note 1)

Inputs

Output

Pin Assignment for SSOP

OEAB

LEAB CLKAB

↓

B₀(Note 2)

B₀(Note 3)

Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,

LEBA, and CLKBA.

Note 2: Output level before the indicated steady-state input conditions

were established.

Note 3: Output level before the indicated steady-state input conditions

were established, provided that CLKAB was LOW before LEAB went LOW.

DS011581.prf

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

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与74ABT16500相关器件

型号	品牌	获取价格	描述	数据表
74ABT16500BDGGRE4	TI	获取价格	ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56
74ABT16500C	NXP	获取价格	18-bit universal bus transceiver 3-State
74ABT16500CDGG	NXP	获取价格	18-bit universal bus transceiver 3-State
74ABT16500CDGG-T	NXP	获取价格	暂无描述
74ABT16500CDG-T	NXP	获取价格	IC ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver
74ABT16500CDL	NXP	获取价格	18-bit universal bus transceiver 3-State
74ABT16500CDL-T	ETC	获取价格	18-Bit Bus Transceiver
74ABT16500CMTD	FAIRCHILD	获取价格	18-Bit Universal Bus Transceivers with 3-STATE Outputs
74ABT16500CMTDX	FAIRCHILD	获取价格	18-Bit Bus Transceiver
74ABT16500CSSC	FAIRCHILD	获取价格	18-Bit Universal Bus Transceivers with 3-STATE Outputs

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