Datasheet > 72V285L20TFGI8

72V285L20TFGI8

更新时间： 2024-11-08 00:45:39

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
25页	205K
描述
3.3 VOLT CMOS SuperSync FIFO

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72V285L20TFGI8 数据手册

3.3 VOLT CMOS SuperSync FIFO™

32,768 x 18

65,536 x 18

IDT72V275

IDT72V285

Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

FEATURES:

• Choose among the following memory organizations:

•

IDT72V275

IDT72V285

32,768 x 18

65,536 x 18

• Green parts are available, see ordering information

• Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

DESCRIPTION:

The IDT72V275/72V285 are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync

FIFOs, including the following:

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheother

has been removed. The Frequency Select pin (FS) has been removed,

thusitisnolongernecessarytoselectwhichofthetwoclockinputs,RCLK

or WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed and short.

• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittento

an empty FIFO to the time it can be read, is now fixed and short. (The

variable clock cycle counting delay associated with the latency period

found on previous SuperSync devices has been eliminated on this

SuperSyncfamily.)

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

•

Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write clocks (permit reading and writing

simultaneously)

SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-

munications,datacommunicationsandotherapplicationsthatneedtobuffer

largeamountsofdata.

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin

FUNCTIONAL BLOCK DIAGRAM

D0 -D17

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

32,768 x 18

65,536 x 18

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

4512 drw 01

Q0 -Q17

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

OCTOBER2014

DSC-4512/4

12 3 4 5 6 7...25

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与72V285L20TFGI8相关器件

型号	品牌	获取价格	描述	数据表
72V291	RENESAS	获取价格	128K x 9 SuperSync FIFO, 3.3V
72V291L10PF8	IDT	获取价格	TQFP-64, Reel
72V291L10PFG	IDT	获取价格	FIFO, 128KX9, 6.5ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
72V291L10PFG8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L10PFGI	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L10PFGI8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L10TF8	IDT	获取价格	TQFP-64, Reel
72V291L10TFG	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L10TFG8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L10TFGI	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO

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