Datasheet > 72V291L20PF8

72V291L20PF8

更新时间： 2024-11-10 07:43:39

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
26页	285K
描述
TQFP-64, Reel

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中文翻译

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数据手册

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72V291L20PF8 数据手册

3.3 VOLT CMOS SuperSync FIFO™

65,536 x 9

131,072 x 9

IDT72V281

IDT72V291

• Independent Read and Write clocks (permit reading and writing

simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin

Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial Temperature Range (-40°C to + 85°C) is available

• Green parts available, see ordering information

FEATURES:

• Choose among the following memory organizations:

IDT72V281

IDT72V291

65,536 x 9

131,072 x 9

• Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable

settings

• Retransmit operation with fixed, low first word data

latency time

DESCRIPTION:

The IDT72V281/72V291 are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync

FIFOs,includingthefollowing:

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is runningatthe higherfrequency.

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First Word • The period required by the retransmit operation is now fixed and short.

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan

emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable

clock cycle counting delay associated with the latency period found on

previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)

FUNCTIONAL BLOCK DIAGRAM

D0-D8

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

65,536 x 9

131,072 x 9

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

Q0-Q8

4513 drw 01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2009

DSC-4513/3

12 3 4 5 6 7...26

中文翻译

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与72V291L20PF8相关器件

型号	品牌	获取价格	描述	数据表
72V291L20PFG	IDT	获取价格	FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64
72V291L20PFG8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L20PFGI	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L20PFGI8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L20TF	IDT	获取价格	TQFP-64, Tray
72V291L20TF8	IDT	获取价格	TQFP-64, Reel
72V291L20TFG	IDT	获取价格	FIFO, 128KX9, 12ns, Synchronous, CMOS, PQFP64, SLIM, TQFP-64
72V291L20TFG8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L20TFGI	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V291L20TFGI8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO

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