Datasheet > 72V295

72V295

更新时间： 2024-11-10 14:58:07

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
27页	386K
描述
128K x 18 SuperSync FIFO, 3.3V

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中文翻译

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数据手册

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72V295 数据手册

3.3 VOLT HIGH DENSITY CMOS

SUPERSYNC FIFO™

131,072 x 18

IDT72V295

IDT72V2105

262,144 x 18

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

• Select IDT Standard timing (using EF and FF flags) or First Word

FEATURES:

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write clocks (permit reading and writing

simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP)

• High-performance submicron CMOS technology

• Green parts available, see ordering information

• Choose among the following memory organizations:

IDT72V295

IDT72V2105

⎯

131,072 x 18

262,144 x 18

• Pin-compatible with the IDT72V255/72V265 and the IDT72V275/

72V285 SuperSync FIFOs

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• 5V input tolerant

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

DESCRIPTION:

The IDT72V295/72V2105 are exceptionally deep, high speed, CMOS

First-In-First-Out(FIFO)memorieswithclockedreadandwritecontrols. These

FIFOsoffernumerousimprovementsoverpreviousSuperSyncFIFOs,includ-

ing the following:

• Partial Reset clears data, but retains programmable settings

• Retransmit operation with fixed, low first word data latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of two preselected offsets

• The limitation of the frequency of one clock input with respect to the other

has been removed. The Frequency Select pin (FS) has been removed,

• Program partial flags by either serial or parallel means

FUNCTIONAL BLOCK DIAGRAM

D0 -D17

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

131,072 x 18

262,144 x 18

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

4668 drw 01

Q0 -Q17

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

MARCH 2018

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4668/7

12 3 4 5 6 7...27

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与72V295相关器件

型号	品牌	获取价格	描述	数据表
72V295L10PF8	IDT	获取价格	TQFP-64, Reel
72V295L15PF8	IDT	获取价格	TQFP-64, Reel
72V295L15PFG	IDT	获取价格	FIFO
72V295L15PFG8	IDT	获取价格	FIFO, 128KX18, 10ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
72V295L15PFGI	IDT	获取价格	FIFO
72V295L15PFGI8	IDT	获取价格	FIFO, 128KX18, 10ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
72V295L15PFI	IDT	获取价格	TQFP-64, Tray
72V295L20PF	IDT	获取价格	TQFP-64, Tray
72V295L20PF8	IDT	获取价格	TQFP-64, Reel
72V295L20PFG	IDT	获取价格	FIFO