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72V291L10TFG PDF预览

72V291L10TFG

更新时间: 2024-11-10 00:47:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
26页 222K
描述
3.3 VOLT CMOS SuperSync FIFO

72V291L10TFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:LFQFP, QFP64,.47SQ,20针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.45
最长访问时间:6.5 ns最大时钟频率 (fCLK):100 MHz
周期时间:10 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e3长度:10 mm
内存密度:1179648 bit内存集成电路类型:OTHER FIFO
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:64
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX9
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.02 A
子类别:FIFOs最大压摆率:0.055 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:10 mm
Base Number Matches:1

72V291L10TFG 数据手册

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3.3 VOLT CMOS SuperSync FIFO™  
65,536 x 9  
131,072 x 9  
IDT72V281  
IDT72V291  
Independent Read and Write clocks (permit reading and writing  
simultaneously)  
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin  
Slim Thin Quad Flat Pack (STQFP)  
High-performance submicron CMOS technology  
Industrial Temperature Range (-40°C to + 85°C) is available  
Green parts available, see ordering information  
FEATURES:  
Choose among the following memory organizations:  
IDT72V281  
IDT72V291  
65,536 x 9  
131,072 x 9  
Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs  
10ns read/write cycle time (6.5ns access time)  
Fixed, low first word data latency time  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable  
settings  
Retransmit operation with fixed, low first word data  
latency time  
DESCRIPTION:  
The IDT72V281/72V291 are exceptionally deep, high speed, CMOS  
First-In-First-Out (FIFO) memories with clocked read and write controls.  
These FIFOs offer numerous improvements over previous SuperSync  
FIFOs,includingthefollowing:  
Empty, Full and Half-Full flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of two preselected offsets  
Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas  
been removed. The Frequency Select pin (FS) has been removed, thus  
it is no longer necessary to select which of the two clock inputs, RCLK or  
WCLK, is running at the higher frequency.  
Program partial flags by either serial or parallel means  
Select IDT Standard timing (using EF and FF flags) or First Word The period required by the retransmit operation is now fixed and short.  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
Easily expandable in depth and width  
Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan  
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable  
clock cycle counting delay associated with the latency period found on  
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)  
FUNCTIONAL BLOCK DIAGRAM  
D0-D8  
WEN  
WCLK  
LD  
SEN  
OFFSET REGISTER  
INPUT REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
HF  
FWFT/SI  
RAM ARRAY  
65,536 x 9  
131,072 x 9  
WRITE POINTER  
READ POINTER  
READ  
CONTROL  
LOGIC  
RT  
OUTPUT REGISTER  
MRS  
PRS  
RESET  
LOGIC  
RCLK  
REN  
Q0-Q8  
4513 drw 01  
OE  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
OCTOBER2014  
1
DSC-4513/4  
©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  

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