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723642L15PF8 PDF预览

723642L15PF8

更新时间: 2023-06-15 00:00:00
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
25页 202K
描述
TQFP-120, Reel

723642L15PF8 数据手册

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CMOS SyncBiFIFOTM  
256 x 36 x 2, 512 x 36 x 2,  
1,024 x 36 x 2  
IDT723622  
IDT723632  
IDT723642  
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-  
saving 120-pin Thin Quad Flatpack (TQFP)  
Low-power 0.8-Micron Advanced CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Greenpartsavailable,seeorderinginformation  
FEATURES:  
Memory storage capacity:  
IDT723622  
IDT723632  
IDT723642  
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
Free-running CLKA and CLKB may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Two independent clocked FIFOs buffering data in opposite  
directions  
DESCRIPTION:  
TheIDT723622/723632/723642areamonolithic,high-speed,low-power,  
CMOSBidirectionalSyncFIFO(clocked)memorywhichsupports clockfre-  
quencies up to 83MHz and have read access times as fast as 8ns. Two  
independent256/512/1,024x36dual-portSRAMFIFOsonboardeachchip  
buffer data in opposite directions. Communication between each port may  
bypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailboxregisterhas  
a flag to signal when new mail has been stored.  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
IRA, ORA, AEA, and AFA flags synchronized by CLKA  
IRB, ORB, AEB, and AFB flags synchronized by CLKB  
Supports clock frequencies up to 83MHz  
Fast access times of 8ns  
These devices are a synchronous (clocked) FIFO, meaning each port  
employsasynchronousinterface.Alldatatransfersthroughaportaregated  
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
MBA  
Port-A  
Control  
Logic  
RAM  
ARRAY  
256 x 36  
512 x 36  
1,024 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
ORB  
AEB  
IRA  
AFA  
FIFO 1  
Programmable Flag  
Offset Registers  
FS  
0
1
B0 - B35  
FS  
A
0
- A35  
10  
FIFO 2  
ORA  
AEA  
Status Flag  
Logic  
IRB  
AFB  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
256 x 36  
512 x 36  
CLKB  
CSB  
Port-B  
Control  
Logic  
1,024 x 36  
W/RB  
ENB  
MBB  
Mail 2  
Register  
3022 drw 01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY 2009  
COMMERCIAL TEMPERATURE RANGE  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3022/5  

723642L15PF8 替代型号

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723642L15PFG8 IDT

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