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723651L15PFG8 PDF预览

723651L15PFG8

更新时间: 2024-11-24 01:17:39
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
20页 347K
描述
CMOS SyncFIFO

723651L15PFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:LFQFP,针数:120
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.32
最长访问时间:11 ns其他特性:MAIL BOX; RETRANSMIT
周期时间:15 nsJESD-30 代码:S-PQFP-G120
JESD-609代码:e3长度:14 mm
内存密度:73728 bit内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:120字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

723651L15PFG8 数据手册

 浏览型号723651L15PFG8的Datasheet PDF文件第2页浏览型号723651L15PFG8的Datasheet PDF文件第3页浏览型号723651L15PFG8的Datasheet PDF文件第4页浏览型号723651L15PFG8的Datasheet PDF文件第5页浏览型号723651L15PFG8的Datasheet PDF文件第6页浏览型号723651L15PFG8的Datasheet PDF文件第7页 
CMOS SyncFIFO™  
512 x 36  
IDT723631  
IDT723641  
IDT723651  
1,024 x 36  
2,048 x 36  
Output Ready (OR) and Almost-Empty (AE) flags synchronized  
by CLKB  
Available in space-saving 120-pin thin quad flat package (TQFP)  
Green parts available, see ordering information  
FEATURES:  
Storage capacity:  
IDT723631 - 512 x 36  
IDT723641 - 1,024 x 36  
IDT723651 - 2,048 x 36  
Supports clock frequencies up to 67 MHz  
Fast access times of 11ns  
DESCRIPTION:  
The IDT723631/723641/723651 is a monolithic high-speed, low-power,  
CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz  
and has read access times as fast as 11ns. The 512/1,024/2,048 x 36  
dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory  
has retransmit capability, which allows previously read data to be ac-  
cessed again. The FIFO has flags to indicate empty and full conditions and  
two programmable flags (Almost-Full and Almost-Empty) to indicate when a  
selected number of words is stored in memory. Communication between  
each port may take place with two 36-bit mailbox registers. Each mailbox  
register has a flag to signal when new mail has been stored. Two or more  
Free-running CLKA and CLKB can be asynchronous or coinci-  
dent (permits simultaneous reading and writing of data on a  
single clock edge)  
Clocked FIFO buffering data from Port A to Port B  
Synchronous read retransmit capability  
Mailbox register in each direction  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor interface control logic  
Input Ready (IR) and Almost-Full (AF) flags synchronized by  
CLKA  
FUNCTIONALBLOCKDIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
MBA  
Port-A  
Control  
Logic  
RAM ARRAY  
512 x 36  
1,024 x 36  
2,048 x 36  
Reset  
Logic  
RST  
RTM  
36  
Read  
Pointer  
Write  
Pointer  
RFM  
A
0
- A35  
B0 - B35  
Status Flag  
OR  
AE  
IR  
AF  
Logic  
FS  
0
/SD  
Flag Offset  
Registers  
FS /SEN  
1
10  
CLKB  
CSB  
W/RB  
ENB  
MBB  
Port-B  
Control  
Logic  
Mail 2  
Register  
3023 drw01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MARCH 2014  
1
©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-2023/8  

723651L15PFG8 替代型号

型号 品牌 替代类型 描述 数据表
723651L15PFG IDT

完全替代

CMOS SyncFIFO

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