Datasheet > 723652L12PQF9

723652L12PQF9

更新时间： 2024-09-27 07:08:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
29页	260K
描述
PQFP-132, Tray

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中文翻译

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数据手册

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723652L12PQF9 数据手册

CMOS SyncBiFIFO^TM

2,048 x 36 x 2

4,096 x 36 x 2

IDT723652

IDT723662

IDT723672

8,192 x 36 x 2

• Select IDT Standard timing (using EFA, EFB, FFA and FFB flags

functions) or First Word Fall Through timing (using ORA, ORB, IRA

and IRB flag functions)

• Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving

120-pin Thin Quad Flatpack (TQFP)

• Pincompatibletothelowerdensityparts,IDT723622/723632/723642

• Industrial temperature range (–40°C to +85°C) is available

FEATURES

• Memory storage capacity:

IDT723652

IDT723662

IDT723672

–

2,048 x 36 x 2

4,096 x 36 x 2

8,192 x 36 x 2

• Supports clock frequencies up to 83MHz

• Fast access times of 8ns

• Free-running CLKA and CLKB may be asynchronous or coincident

(simultaneous reading and writing of data on a single clock edge

is permitted)

DESCRIPTION

TheIDT723652/723662/723672isamonolithic,high-speed,low-power,

• Two independent clocked FIFOs buffering data in opposite direc- CMOS Bidirectional SyncFIFO (clocked) memories which support clock

tions

frequencies up to 83MHz and have read access times as fast as 8ns. Two

independent2,048/4,096/8,192x36dual-portSRAMFIFOs onboardeach

chipbufferdatainoppositedirections. Communicationbetweeneachportmay

bypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailboxregisterhas

a flag to signal when new mail has been stored.

• Mailbox bypass register for each FIFO

• Programmable Almost-Full and Almost-Empty flags

• Microprocessor Interface Control Logic

• FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA

• FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

CSA

W/RA

ENA

MBA

Port-A

Control

Logic

RAM

ARRAY

2,048 x 36

4,096 x 36

8,192 x 36

FIFO1,

Mail1

Reset

Logic

RST1

Write

Pointer

Read

Pointer

Status Flag

Logic

EFB/ORB

AEB

FFA/IRA

AFA

FIFO 1

Programmable Flag

Offset Registers

Timing

Mode

FWFT

- A35

B0 - B35

FIFO 2

Status Flag

EFA/ORA

FFB/IRB

AFB

Logic

AEA

Read

Pointer

Write

Pointer

FIFO2,

Mail2

Reset

Logic

RST2

RAM

ARRAY

2,048 x 36

4,096 x 36

8,192 x 36

CLKB

CSB

W/RB

ENB

MBB

Port-B

Control

Logic

Mail 2

5609 drw 01

MBF2

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIAL TEMPERATURE RANGE

NOVEMBER 2003



DSC-5609/4

12 3 4 5 6 7...29

中文翻译

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与723652L12PQF9相关器件

型号	品牌	获取价格	描述	数据表
723652L12PQFG	IDT	获取价格	Bi-Directional FIFO, 2KX36, 8ns, Synchronous, CMOS, PQFP132, GREEN, PLASTIC, QFP-132
723652L15PFG	IDT	获取价格	CMOS SyncBiFIFOTM
723652L15PQF8	IDT	获取价格	PQFP-132, Reel
723652L15PQFG	IDT	获取价格	CMOS SyncBiFIFOTM
723653L12	IDT	获取价格	CMOS SyncFIFOTM WITH BUS-MATCHING
723653L12PF	IDT	获取价格	TQFP-128, Tray
723653L12PF8	IDT	获取价格	TQFP-128, Reel
723653L12PF9	IDT	获取价格	TQFP-128, Tray
723653L12PFG	IDT	获取价格	FIFO, 2KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128
723653L15	IDT	获取价格	CMOS SyncFIFOTM WITH BUS-MATCHING

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