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723656L20PF PDF预览

723656L20PF

更新时间: 2024-11-14 21:02:51
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
39页 352K
描述
Bi-Directional FIFO, 4KX36, 12ns, Synchronous, CMOS, PQFP128

723656L20PF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.92
最长访问时间:12 ns最大时钟频率 (fCLK):50 MHz
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
内存密度:147456 bit内存集成电路类型:BI-DIRECTIONAL FIFO
内存宽度:36湿度敏感等级:3
端子数量:128字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX36封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP128,.63X.87,20
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified最大待机电流:0.001 A
子类别:FIFOs标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:6
Base Number Matches:1

723656L20PF 数据手册

 浏览型号723656L20PF的Datasheet PDF文件第2页浏览型号723656L20PF的Datasheet PDF文件第3页浏览型号723656L20PF的Datasheet PDF文件第4页浏览型号723656L20PF的Datasheet PDF文件第5页浏览型号723656L20PF的Datasheet PDF文件第6页浏览型号723656L20PF的Datasheet PDF文件第7页 
CMOS TRIPLE BUS SyncFIFOTM  
WITH BUS-MATCHING  
2,048 x 36 x 2, 4,096 x 36 x 2,  
8,192 x 36 x 2  
PRELIMINARY  
IDT723656  
IDT723666  
IDT723676  
five default offsets (8, 16, 64, 256 and 1024)  
FEATURES:  
Serial or parallel programming of partial flags  
Big- or Little-Endian format for word and byte bus sizes  
Loopback mode on Port A  
Retransmit Capability  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
Memory storage capacity:  
IDT723656  
IDT723666  
IDT723676  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
Clock frequencies up to 83 MHz (8ns access time)  
Two independent FIFOs buffer data between one bidirectional  
36-bit port and two unidirectional 18-bit ports (Port C receives  
and Port B transmits)  
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on  
Ports B and C  
Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRC flag functions)  
Mailbox bypass registers for each FIFO  
Free-running CLKA, CLKB and CLKC may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin compatible to the lower density parts, IDT723626/3636/3646  
Industrial temperature range (–40°C to +85°C) is available  
Programmable Almost-Empty and Almost-Full flags; each has  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
CLKA  
CSA  
W/RA  
ENA  
MBA  
LOOP  
Register  
Port-A  
Control  
Logic  
18  
B0-B17  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
36  
36  
CLKB  
RENB  
CSB  
Port-B  
Control  
Logic  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
MBB  
Read  
Pointer  
Write  
Pointer  
SIZEB  
36  
Status Flag  
Logic  
FFA/IRA  
EFB/ORB  
AFA  
AEB  
FIFO1  
FIFO2  
Common  
Port  
FS2  
FS0/SD  
Control  
Logic  
Programmable Flag  
Offset Registers  
Timing  
Mode  
BE  
FS1/SEN  
(B and C)  
A0-A35  
13  
FWFT  
FFC/IRC  
AFC  
Status Flag  
Logic  
EFA/ORA  
AEA  
Read  
Pointer  
Write  
Pointer  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
36  
RT1  
RTM  
RT2  
FIFO1 and  
FIFO2  
Retransmit  
Logic  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
18  
36  
36  
C0-C17  
CLKC  
WENC  
MBC  
Port-C  
Control  
Logic  
Mail 2  
Register  
SIZEC  
5611 drw01  
MBF2  
TheSyncFIFOisatrademarkandtheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
MARCH 2001  
COMMERCIAL TEMPERATURE RANGE  
1
2001 Integrated Device Technology, Inc.  
DSC-5611/2  

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