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723662L12PF PDF预览

723662L12PF

更新时间: 2024-11-14 19:12:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
29页 260K
描述
TQFP-120, Tray

723662L12PF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:TQFP-120针数:120
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.92
最长访问时间:8 ns其他特性:MAIL BOX
最大时钟频率 (fCLK):83 MHz周期时间:12 ns
JESD-30 代码:S-PQFP-G120JESD-609代码:e0
长度:14 mm内存密度:147456 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
湿度敏感等级:4功能数量:1
端子数量:120字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP120,.63SQ,16封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.001 A子类别:FIFOs
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

723662L12PF 数据手册

 浏览型号723662L12PF的Datasheet PDF文件第2页浏览型号723662L12PF的Datasheet PDF文件第3页浏览型号723662L12PF的Datasheet PDF文件第4页浏览型号723662L12PF的Datasheet PDF文件第5页浏览型号723662L12PF的Datasheet PDF文件第6页浏览型号723662L12PF的Datasheet PDF文件第7页 
CMOS SyncBiFIFOTM  
2,048 x 36 x 2  
4,096 x 36 x 2  
IDT723652  
IDT723662  
IDT723672  
8,192 x 36 x 2  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving  
120-pin Thin Quad Flatpack (TQFP)  
Pincompatibletothelowerdensityparts,IDT723622/723632/723642  
Industrial temperature range (–40°C to +85°C) is available  
FEATURES  
Memory storage capacity:  
IDT723652  
IDT723662  
IDT723672  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
Supports clock frequencies up to 83MHz  
Fast access times of 8ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
DESCRIPTION  
TheIDT723652/723662/723672isamonolithic,high-speed,low-power,  
Two independent clocked FIFOs buffering data in opposite direc- CMOS Bidirectional SyncFIFO (clocked) memories which support clock  
tions  
frequencies up to 83MHz and have read access times as fast as 8ns. Two  
independent2,048/4,096/8,192x36dual-portSRAMFIFOs onboardeach  
chipbufferdatainoppositedirections. Communicationbetweeneachportmay  
bypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailboxregisterhas  
a flag to signal when new mail has been stored.  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
MBA  
Port-A  
Control  
Logic  
RAM  
ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS  
0
1
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS  
A
0
- A35  
13  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
CLKB  
CSB  
W/RB  
ENB  
MBB  
Port-B  
Control  
Logic  
Mail 2  
Register  
5609 drw 01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
NOVEMBER 2003  
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5609/4  

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