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723656L15PF8 PDF预览

723656L15PF8

更新时间: 2024-11-15 04:31:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
39页 336K
描述
TQFP-128, Reel

723656L15PF8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:TQFP-128针数:128
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.92
最长访问时间:10 ns其他特性:MAILBOX
最大时钟频率 (fCLK):66.7 MHz周期时间:15 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
长度:20 mm内存密度:73728 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:2048 words
字数代码:2000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.001 A子类别:FIFOs
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

723656L15PF8 数据手册

 浏览型号723656L15PF8的Datasheet PDF文件第2页浏览型号723656L15PF8的Datasheet PDF文件第3页浏览型号723656L15PF8的Datasheet PDF文件第4页浏览型号723656L15PF8的Datasheet PDF文件第5页浏览型号723656L15PF8的Datasheet PDF文件第6页浏览型号723656L15PF8的Datasheet PDF文件第7页 
CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
IDT723656  
IDT723666  
IDT723676  
Serial or parallel programming of partial flags  
Big- or Little-Endian format for word and byte bus sizes  
Loopback mode on Port A  
Retransmit Capability  
Master Reset clears data and configures FIFO, Partial Reset  
clears data but retains configuration settings  
FEATURES  
Memory storage capacity:  
IDT723656  
IDT723666  
IDT723676  
2,048 x 36 x 2  
4,096 x 36 x 2  
8,192 x 36 x 2  
Clock frequencies up to 83 MHz (8ns access time)  
Two independent FIFOs buffer data between one bidirectional  
36-bit port and two unidirectional 18-bit ports (Port C receives  
and Port B transmits)  
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on  
Ports B and C  
Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag  
functions) or First Word Fall Through Timing (using ORA, ORB,  
IRA, and IRC flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
five default offsets (8, 16, 64, 256 and 1024)  
Mailbox bypass registers for each FIFO  
Free-running CLKA, CLKB and CLKC may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Pin compatible to the lower density parts, IDT723626/3636/3646  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
CLKA  
CSA  
W/RA  
ENA  
MBA  
LOOP  
Register  
Port-A  
Control  
Logic  
18  
B0-B17  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
36  
36  
CLKB  
Port-B  
FIFO1,  
Mail1  
Reset  
Logic  
MRS1  
PRS1  
RENB  
Control  
CSB  
MBB  
Logic  
Read  
Pointer  
Write  
Pointer  
SIZEB  
36  
Status Flag  
Logic  
FFA/IRA  
EFB/ORB  
AFA  
AEB  
FIFO1  
FIFO2  
Common  
Port  
FS2  
FS0/SD  
FS1/SEN  
A0-A35  
Control  
Logic  
Programmable Flag  
Offset Registers  
Timing  
Mode  
BE  
(B and C)  
13  
FWFT  
FFC/IRC  
AFC  
Status Flag  
Logic  
EFA/ORA  
AEA  
Read  
Pointer  
Write  
Pointer  
FIFO2,  
Mail2  
Reset  
Logic  
MRS2  
PRS2  
36  
RT1  
RTM  
RT2  
FIFO1 and  
FIFO2  
Retransmit  
Logic  
RAM ARRAY  
2,048 x 36  
4,096 x 36  
8,192 x 36  
18  
36  
36  
C0-C17  
CLKC  
WENC  
MBC  
Port-C  
Control  
Logic  
Mail 2  
Register  
SIZEC  
5611 drw01  
MBF2  
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc.NSynGcFEIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY 2009  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5611/6  

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