Datasheet > 723646L12PFG

723646L12PFG

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
35页	340K
描述
FIFO, 1KX36, 8ns, Synchronous, CMOS, PQFP128, TQFP-128

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数据手册

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723646L12PFG 数据手册

CMOS TRIPLE BUS SyncFIFO^TM

WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2

1,024 x 36 x 2

IDT723626

IDT723636

IDT723646

• Serial or parallel programming of partial flags

FEATURES:

• Big- or Little-Endian format for word and byte bus sizes

• Master Reset clears data and configures FIFO, Partial Reset

clears data but retains configuration settings

• Memory storage capacity:

IDT723626 – 256 x 36 x 2

IDT723636 – 512 x 36 x 2

IDT723646 – 1,024 x 36 x 2

• Mailbox bypass registers for each FIFO

• Free-running CLKA, CLKB and CLKC may be asynchronous or

coincident (simultaneous reading and writing of data on a single

clock edge is permitted)

• Auto power down minimizes power dissipation

• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

• Clock frequencies up to 83 MHz (8ns access time)

• Two independent FIFOs buffer data between one bidirectional

36-bit port and two unidirectional 18-bit ports (Port C receives

and Port B transmits)

• 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on

Ports B and C

• Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag

functions) or First Word Fall Through Timing (using ORA, ORB,

IRA, and IRC flag functions)

• Programmable Almost-Empty and Almost-Full flags; each has

three default offsets (8, 16 and 64)

•

Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

DESCRIPTION:

TheIDT723626/723636/723646isamonolithic,high-speed,low-power,

CMOSTripleBussynchronous(clocked)FIFOmemorywhichsupportsclock

FUNCTIONAL BLOCK DIAGRAM

MBF1

Mail 1

CLKA

CSA

Port-A

W/RA

Control

B0-B17

ENA

MBA

RAM ARRAY

256 x 36

Logic

512 x 36

1,024 x 36

CLKB

RENB

CSB

MBB

SIZEB

FIFO1,

Mail1

Reset

Logic

Port-B

Control

Logic

MRS1

PRS1

Write

Pointer

Read

Pointer

Status Flag

Logic

EFB/ORB

FFA/IRA

AEB

AFA

FIFO1

FIFO2

Common

Port

SPM

FS0/SD

Programmable Flag

Offset Registers

Control

Logic

Timing

Mode

FS1/SEN

(B and C)

A -A35

FWFT

FFC/IRC

AFC

Status Flag

Logic

EFA/ORA

AEA

Read

Pointer

Write

Pointer

FIFO2,

Mail2

Reset

Logic

MRS2

PRS2

RAM ARRAY

256 x 36

C -C17

512 x 36

1,024 x 36

CLKC

WENC

MBC

Port-C

Control

Logic

SIZEC

Mail 2

MBF2

3271 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

COMMERCIALTEMPERATURERANGE

FEBRUARY 2009

DSC-3271/5

12 3 4 5 6 7...35

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与723646L12PFG相关器件

型号	品牌	获取价格	描述	数据表
723646L15PFG	IDT	获取价格	FIFO, 1KX36, 10ns, Synchronous, CMOS, PQFP128, TQFP-128
723646L20PF	IDT	获取价格	Bi-Directional FIFO, 2KX36, 12ns, Synchronous, CMOS, PQFP128
723646L30PF	IDT	获取价格	Bi-Directional FIFO, 2KX36, 15ns, Synchronous, CMOS, PQFP128
7236-47	MOLEX	获取价格	Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)
7236-50	MOLEX	获取价格	Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)
723651	RENESAS	获取价格	2K x 36 SyncFIFO, 5.0V
723651L15PF9	IDT	获取价格	FIFO, 2KX36, 11ns, Synchronous, CMOS, PQFP120, TQFP-120
723651L15PFG	IDT	获取价格	CMOS SyncFIFO
723651L15PFG8	IDT	获取价格	CMOS SyncFIFO
723651L15PFGI	IDT	获取价格	FIFO, 2KX36, 11ns, Synchronous, CMOS, PQFP120, TQFP-120

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