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723631L20PF8

更新时间： 2023-07-15 00:00:00

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723631L20PF8 数据手册

IDT723631/723641/723651 CMOS SyncFIFO™

512 x 36, 1,024 x 36 and 2,048 x 36

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

250

fdata = 1/2 fS

= 25°C

= 0pF

VCC = 5.5V

200

150

100

VCC = 5.0V

VCC= 4.5V

3023 drw04

⎯ Clock Frequency ⎯ MHz

Figure 1. Typical Characteristics: Supply vs Clock Frequency

CALCULATING POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723641 with CLKA and CLKB set

to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to

normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT723631/723641/723651

inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:

PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC x fO)

where:

∆ICC

number of inputs driven by TTL levels

increase in power supply current for each input at a TTL HIGH level

duty cycle of inputs at a TTL HIGH level of 3.4

output capacitance load

switching frequency of an output

When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is

calculated by:

PT = VCC x fS x 0.209 mA/MHz

1...3 4 567 8 9...21

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型号	品牌	描述	获取价格	数据表
723631L20PFG	IDT	FIFO, 512X36, 13ns, Synchronous, CMOS, PQFP120, TQFP-120	获取价格
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723631L20PFGI	IDT	TQFP-120, Tray	获取价格
723631L20PFI9	IDT	FIFO, 512X36, 13ns, Synchronous, CMOS, PQFP120, TQFP-120	获取价格
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