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723633L12PFG PDF预览

723633L12PFG

更新时间: 2024-11-20 01:19:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片配套器件内存集成电路
页数 文件大小 规格书
28页 463K
描述
CMOS BUS-MATCHING SyncFIFO

723633L12PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:LFQFP, QFP128,.63X.87,20针数:128
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.68
最长访问时间:8 ns其他特性:MAIL BOX
最大时钟频率 (fCLK):83 MHz周期时间:12 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e3
长度:20 mm内存密度:18432 bit
内存集成电路类型:OTHER FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:512 words
字数代码:512工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512X36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.001 A子类别:FIFOs
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

723633L12PFG 数据手册

 浏览型号723633L12PFG的Datasheet PDF文件第2页浏览型号723633L12PFG的Datasheet PDF文件第3页浏览型号723633L12PFG的Datasheet PDF文件第4页浏览型号723633L12PFG的Datasheet PDF文件第5页浏览型号723633L12PFG的Datasheet PDF文件第6页浏览型号723633L12PFG的Datasheet PDF文件第7页 
CMOS BUS-MATCHING SyncFIFOTM  
256 x 36, 512 x 36, 1,024 x 36  
IDT723623  
IDT723633  
IDT723643  
Reset clears data and configures FIFO, Partial Reset clears data  
but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
FEATURES:  
Memory storage capacity:  
IDT723623  
IDT723633  
IDT723643  
256 x 36  
512 x 36  
1,024 x 36  
Clocked FIFO buffering data from Port A to Port B  
Clock frequencies up to 83 MHz (8 ns access time)  
IDT Standard timing (using EF and FF) or First Word Fall  
Through Timing (using OR and IR flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
Serial or parallel programming of partial flags  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Easily expandable in width and depth  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Green parts available, see ordering information  
DESCRIPTION:  
TheIDT723623/723633/723643aremonolithic,high-speed,low-power,  
CMOSunidirectionalSynchronous(clocked)FIFOmemorieswhichsupport  
clock frequencies up to 83 MHz and have read access times as fast as 8 ns.  
Big- or Little-Endian format for word and byte bus sizes  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
Port-A  
Control  
Logic  
MBA  
36  
RAM ARRAY  
256 x 36  
36  
36  
FIFO1  
Mail1,  
Mail2,  
Reset  
Logic  
RS1  
RS2  
PRS  
512 x 36  
1,024 x 36  
36  
Write  
Pointer  
Read  
Pointer  
A0-A35  
B0-B35  
Status Flag  
Logic  
EF/OR  
AE  
FF/IR  
AF  
36  
36  
SPM  
FS0/SD  
FS1/SEN  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
10  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
BM  
SIZE  
Mail 2  
Register  
3269 drw01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
MARCH 2014  
1
©
2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3269/5  

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