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723633L20PF PDF预览

723633L20PF

更新时间: 2024-11-19 18:10:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
28页 240K
描述
FIFO, 512X36, 12ns, Synchronous, CMOS, PQFP128

723633L20PF 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.76最长访问时间:12 ns
最大时钟频率 (fCLK):50 MHzJESD-30 代码:R-PQFP-G128
JESD-609代码:e0内存密度:18432 bit
内存集成电路类型:OTHER FIFO内存宽度:36
湿度敏感等级:3端子数量:128
字数:512 words字数代码:512
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512X36
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
子类别:FIFOs标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:6
Base Number Matches:1

723633L20PF 数据手册

 浏览型号723633L20PF的Datasheet PDF文件第2页浏览型号723633L20PF的Datasheet PDF文件第3页浏览型号723633L20PF的Datasheet PDF文件第4页浏览型号723633L20PF的Datasheet PDF文件第5页浏览型号723633L20PF的Datasheet PDF文件第6页浏览型号723633L20PF的Datasheet PDF文件第7页 
CMOS BUS-MATCHING SyncFIFOTM  
256 x 36, 512 x 36, 1,024 x 36  
IDT723623  
IDT723633  
IDT723643  
Reset clears data and configures FIFO, Partial Reset clears data  
but retains configuration settings  
Mailbox bypass registers for each FIFO  
Free-running CLKA and CLKB may be asynchronous or  
coincident (simultaneous reading and writing of data on a single  
clock edge is permitted)  
FEATURES:  
Memory storage capacity:  
IDT723623  
IDT723633  
IDT723643  
256 x 36  
512 x 36  
1,024 x 36  
Clocked FIFO buffering data from Port A to Port B  
Clock frequencies up to 83 MHz (8 ns access time)  
IDT Standard timing (using EF and FF) or First Word Fall  
Through Timing (using OR and IR flag functions)  
Programmable Almost-Empty and Almost-Full flags; each has  
three default offsets (8, 16 and 64)  
Easily expandable in width and depth  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
Industrial temperature range (–40°C to +85°C) is available  
DESCRIPTION:  
TheIDT723623/723633/723643aremonolithic,high-speed,low-power,  
CMOSunidirectionalSynchronous(clocked)FIFOmemorieswhichsupport  
clockfrequencies upto83MHzandhave readaccess times as fastas 8ns.  
Serial or parallel programming of partial flags  
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits  
(byte)  
Big- or Little-Endian format for word and byte bus sizes  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
Port-A  
Control  
Logic  
MBA  
36  
RAM ARRAY  
256 x 36  
36  
36  
FIFO1  
Mail1,  
Mail2,  
Reset  
Logic  
RS1  
RS2  
PRS  
512 x 36  
1,024 x 36  
36  
Write  
Pointer  
Read  
Pointer  
A0-A35  
B0-B35  
Status Flag  
Logic  
EF/OR  
AE  
FF/IR  
AF  
36  
36  
SPM  
FS0/SD  
FS1/SEN  
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
10  
CLKB  
CSB  
W/RB  
ENB  
MBB  
BE  
Port-B  
Control  
Logic  
BM  
SIZE  
Mail 2  
Register  
3269 drw01  
MBF2  
TheSyncFIFOisatrademarkandtheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
MARCH 2001  
1
2001 Integrated Device Technology, Inc.  
DSC-3269/1  

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