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723632L15PFG PDF预览

723632L15PFG

更新时间: 2024-01-26 04:28:34
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
24页 188K
描述
CMOS SyncBiFIFO

723632L15PFG 数据手册

 浏览型号723632L15PFG的Datasheet PDF文件第2页浏览型号723632L15PFG的Datasheet PDF文件第3页浏览型号723632L15PFG的Datasheet PDF文件第4页浏览型号723632L15PFG的Datasheet PDF文件第5页浏览型号723632L15PFG的Datasheet PDF文件第6页浏览型号723632L15PFG的Datasheet PDF文件第7页 
CMOS SyncBiFIFOTM  
256 x 36 x 2, 512 x 36 x 2,  
1,024 x 36 x 2  
IDT723622  
IDT723632  
IDT723642  
Fast access times of 10ns  
Available in space-saving 120-pin Thin Quad Flatpack (TQFP)  
Green parts available  
FEATURES:  
Memory storage capacity:  
IDT723622  
IDT723632  
IDT723642  
256 x 36 x 2  
512 x 36 x 2  
1,024 x 36 x 2  
DESCRIPTION:  
Free-running CLKA and CLKB may be asynchronous or  
TheIDT723622/723632/723642areamonolithic,high-speed,low-power,  
coincident (simultaneous reading and writing of data on a single CMOS Bidirectional SyncFIFO (clocked) memory which supports clock fre-  
clock edge is permitted)  
Two independent clocked FIFOs buffering data in opposite  
directions  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
IRA, ORA, AEA, and AFA flags synchronized by CLKA  
IRB, ORB, AEB, and AFB flags synchronized by CLKB  
Supports clock frequencies up to 66.7MHz  
quencies up to 66.7MHz and have read access times as fast as 10ns.  
Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board  
each chip buffer data in opposite directions. Communication between  
each port may bypass the FIFOs via two 36-bit mailbox registers. Each  
mailbox register has a flag to signal when new mail has been stored.  
These devices are a synchronous (clocked) FIFO, meaning each port  
employsasynchronousinterface.Alldatatransfersthroughaportaregated  
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor  
each port are independent of one another and can be asynchronous or  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
Port-A  
Control  
Logic  
CSA  
W/RA  
ENA  
RAM  
ARRAY  
MBA  
256 x 36  
512 x 36  
1,024 x 36  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
ORB  
AEB  
IRA  
AFA  
FIFO 1  
Programmable Flag  
Offset Registers  
FS  
0
1
B0 - B35  
FS  
A
0
- A35  
10  
FIFO 2  
ORA  
AEA  
Status Flag  
Logic  
IRB  
AFB  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
256 x 36  
512 x 36  
CLKB  
CSB  
Port-B  
Control  
Logic  
1,024 x 36  
W/RB  
ENB  
MBB  
Mail 2  
Register  
3022 drw 01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY2015  
COMMERCIAL TEMPERATURE RANGE  
1
©
2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3022/6  

723632L15PFG 替代型号

型号 品牌 替代类型 描述 数据表
723642L15PFG IDT

完全替代

CMOS SyncBiFIFO
723651L15PFG IDT

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CMOS SyncFIFO

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