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723631L20PQFI PDF预览

723631L20PQFI

更新时间: 2024-11-20 07:16:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
21页 216K
描述
PQFP-132, Tray

723631L20PQFI 数据手册

 浏览型号723631L20PQFI的Datasheet PDF文件第2页浏览型号723631L20PQFI的Datasheet PDF文件第3页浏览型号723631L20PQFI的Datasheet PDF文件第4页浏览型号723631L20PQFI的Datasheet PDF文件第5页浏览型号723631L20PQFI的Datasheet PDF文件第6页浏览型号723631L20PQFI的Datasheet PDF文件第7页 
CMOS SyncFIFO™  
512 x 36  
IDT723631  
IDT723641  
IDT723651  
1,024 x 36  
2,048 x 36  
Output Ready (OR) and Almost-Empty (AE) flags synchronized  
by CLKB  
Available in 132-pin plastic quad flat package (PQFP) or space-  
saving 120-pin thin quad flat package (TQFP)  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FEATURES:  
Storage capacity:  
IDT723631 - 512 x 36  
IDT723641 - 1,024 x 36  
IDT723651 - 2,048 x 36  
Supports clock frequencies up to 67 MHz  
Fast access times of 11ns  
DESCRIPTION:  
Free-running CLKA and CLKB can be asynchronous or coinci-  
dent (permits simultaneous reading and writing of data on a  
single clock edge)  
Clocked FIFO buffering data from Port A to Port B  
Synchronous read retransmit capability  
Mailbox register in each direction  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor interface control logic  
Input Ready (IR) and Almost-Full (AF) flags synchronized by  
CLKA  
The IDT723631/723641/723651 is a monolithic high-speed, low-power,  
CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz  
and has read access times as fast as 12ns. The 512/1,024/2,048 x 36  
dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory  
has retransmit capability, which allows previously read data to be ac-  
cessed again. The FIFO has flags to indicate empty and full conditions and  
two programmable flags (Almost-Full and Almost-Empty) to indicate when a  
selected number of words is stored in memory. Communication between  
each port may take place with two 36-bit mailbox registers. Each mailbox  
FUNCTIONALBLOCKDIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
W/RA  
ENA  
MBA  
Port-A  
Control  
Logic  
RAM ARRAY  
512 x 36  
1,024 x 36  
2,048 x 36  
Reset  
Logic  
RST  
RTM  
36  
Read  
Pointer  
Write  
Pointer  
RFM  
A
0
- A35  
B0 - B35  
Status Flag  
OR  
AE  
IR  
AF  
Logic  
FS  
0
/SD  
Flag Offset  
Registers  
FS /SEN  
1
10  
CLKB  
CSB  
W/RB  
ENB  
MBB  
Port-B  
Control  
Logic  
Mail 2  
Register  
3023 drw01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
FEBRUARY 2009  
1
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-2023/7  

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