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723631L15PQF9 PDF预览

723631L15PQF9

更新时间: 2023-01-03 00:14:55
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
21页 219K
描述
FIFO, 512X36, 11ns, Synchronous, CMOS, PQFP132, PLASTIC, QFP-132

723631L15PQF9 数据手册

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IDT723631/723641/723651 CMOS SyncFIFO™  
512 x 36, 1,024 x 36 and 2,048 x 36  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
250  
fdata = 1/2 fS  
TA  
= 25°C  
CL  
= 0pF  
VCC = 5.5V  
200  
150  
100  
50  
VCC = 5.0V  
VCC= 4.5V  
0
0
10  
20  
30  
40  
50  
60  
70  
3023 drw04  
fS  
Clock Frequency MHz  
Figure 1. Typical Characteristics: Supply vs Clock Frequency  
CALCULATING POWER DISSIPATION  
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723641 with CLKA and CLKB set  
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to  
normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT723631/723641/723651  
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.  
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:  
2
PT = VCC x [ICC(f) + (N x ICC x dc)] + Σ(CL x VCC x fO)  
where:  
N
ICC  
dc  
CL  
fO  
=
=
=
=
=
number of inputs driven by TTL levels  
increase in power supply current for each input at a TTL HIGH level  
duty cycle of inputs at a TTL HIGH level of 3.4  
output capacitance load  
switching frequency of an output  
When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is  
calculated by:  
PT = VCC x fS x 0.209 mA/MHz  
6

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