IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
another and can be asynchronous or coincident. The enables for each
port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are
two-stage synchronized to CLKA. The Output Ready (OR) flag and Al-
most-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB.
Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be
programmed from port A or through a serial input.
DESCRIPTION(CONTINUED)
register has a flag to signal when new mail has been stored. Two or more
devices may be used in parallel to create wider data paths. Expansion is
also possible in word depth.
These devices are a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the
LOW-to-HIGH transition of a continuous (free-running) port clock by en-
able signals. The continuous clocks for each port are independent of one
PINCONFIGURATION
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NC
NC
B
B
B
B
35
34
33
32
*
A
A
A
A
V
A
A
35
34
33
32
CC
31
30
GND
B
B
B
B
B
B
31
30
29
28
27
26
GND
A
A
A
A
A
A
A
29
28
27
26
25
24
23
V
CC
B
25
B24
GND
B
B
B
B
B
B
23
22
21
20
19
18
GND
98
A
V
A
A
A
A
22
CC
21
20
19
18
97
96
95
GND
94
B
17
16
93
B
92
GND
V
CC
91
A
A
A
A
A
V
A
17
16
15
14
13
CC
12
B
15
14
13
12
90
B
B
B
89
88
87
GND
NC
86
85
NC
84
NC
3023 drw02
* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
NOTES:
1. NC – No Connection
2. Uses Yamaichi socket IC51-1324-828
PQFP (PQ132-1, ORDER CODE: PQF)
TOP VIEW
2