IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION
Symbol
A0-A35
AE
Name
I/O
I/O
O
Description
Port-AData
36-bitbidirectionaldataportforsideA.
Almost-Empty
Flag
Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to the value in
theAlmost-Emptyregister(X).
AF
Almost-Full
Flag
O
Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO is less than or equal to the
valueintheAlmost-FullOffsetregister(Y).
B0-B35
CLKA
Port-BData
I/O
I
36-bitbidirectionaldataportforsideB.
Port-A Clock
CLKAisacontinuousclockthatsynchronizesalldatatransfersthroughport-AandmaybeasynchronousorcoincidenttoCLKB.
IR and AF are synchronous to the LOW-to-HIGH transition of CLKA.
CLKB
CSA
CSB
Port-B Clock
I
I
I
CLKBisacontinuousclockthatsynchronizesalldatatransfersthroughport-BandmaybeasynchronousorcoincidenttoCLKA.
OR and AE are synchronous to the LOW-to-HIGH transition of CLKB.
Port-A Chip
Select
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 outputs are in the
high-impedance state when CSA is HIGH.
Port-B Chip
Select
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 outputs are in the
high-impedance state when CSB is HIGH.
ENA
ENB
Port-AEnable
Port-BEnable
I
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FS1/
SEN,
Flag-Offset
Select1/
SerialEnable
FS1/SENandFS0/SDaredual-purposeinputsusedforflagOffsetregisterprogramming.Duringadevicereset,FS1/SENand
FS0/SDselectstheflagoffsetprogrammingmethod.ThreeOffsetregisterprogrammingmethodsareavailable:automatically
loadoneoftwopresetvalues, parallelloadfromportA, andserialload.
FS0/SD
IR
FlagOffset0/
SerialData
WhenserialloadisselectedforflagOffsetregisterprogramming,FS1/SENisusedasanenablesynchronoustotheLOW-to-
HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X and Y
registers.ThenumberofbitwritesrequiredtoprogramtheOffsetregistersis18/20/22.ThefirstbitwritestorestheY-register
MSB and the last bit write stores the X-register LSB.
InputReady
Flag
O
IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array are
disabled.WhentheFIFOisinretransmitmode,IRindicateswhenthememoryhasbeenfilledtothepointoftheretransmit
dataandpreventsfurtherwrites. IR is set LOW during reset and is set HIGH after reset.
MBA
MBB
MBF1
MBF2
OR
Port-A Mailbox
Select
I
A HIGH level chooses a mailbox register for a port-A read or write operation.
Port-B Mailbox
Select
I
A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH
levelonMBBselectsdatafromthemail1registerforoutputandaLOWlevelselectsFIFOdataforoutput.
Mail1Register
Flag
O
O
O
MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH by a
LOW-to-HIGH transition of CLKB when a port-B readis selected and MBB is HIGH. MBF1 is set HIGH by a reset.
Mail2Register
Flag
MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register. MBF2 is set HIGH by a
LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH by a reset.
OutputReady
Flag
OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are disabled.
Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the reset and goes
HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory.
RFM
RST
RTM
ReadFrom
Mark
I
I
I
When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-HIGH transition of CLKB to reset the read pointer
tothebeginningretransmitlocationandoutputthefirstselectedretransmitdata.
Reset
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST
is LOW. The LOW-to-HIGH transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.
Retransmit
Mode
When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition of CLKB
selectsthedataforthebeginningofaretransmitandputstheFIFOinretransmitmode.Theselectedwordremainstheinitial
retransmit point until a LOW- to-HIGH transition of CLKB occurs while RTM is LOW, taking the FIFO out of retransmit mode.
W/RA
W/RB
Port-AWrite/
ReadSelect
I
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The
A0-A35 outputs are in the high-impedance state when W/RA is HIGH.
Port-BWrite/
ReadSelect
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The
B0-B35outputsareinthehigh-impedancestatewhenW/RBisLOW.
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