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71V546XS117PFG PDF预览

71V546XS117PFG

更新时间: 2024-02-09 03:24:57
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
21页 164K
描述
3.3V Synchronous SRAM

71V546XS117PFG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:QFP, QFP100,.63X.87
Reach Compliance Code:compliant风险等级:5.56
最长访问时间:4.5 ns最大时钟频率 (fCLK):117 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e3内存密度:4718592 bit
内存集成电路类型:ZBT SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified最大待机电流:0.04 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.275 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

71V546XS117PFG 数据手册

 浏览型号71V546XS117PFG的Datasheet PDF文件第2页浏览型号71V546XS117PFG的Datasheet PDF文件第3页浏览型号71V546XS117PFG的Datasheet PDF文件第4页浏览型号71V546XS117PFG的Datasheet PDF文件第6页浏览型号71V546XS117PFG的Datasheet PDF文件第7页浏览型号71V546XS117PFG的Datasheet PDF文件第8页 
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with  
ZBTFeature, Burst Counter and Pipelined Outputs  
Commercial and Industrial Temperature Ranges  
AbsoluteMaximumRatings(1)  
RecommendedDCOperating  
Conditions  
Commercial &  
Symbol  
Rating  
Unit  
Industrial Values  
Symbol  
Parameter  
Min. Typ.  
Max.  
3.465  
0
Unit  
V
(2)  
V
V
TERM  
Terminal Voltage  
-0.5 to +4.6  
V
(3)  
V
DD  
Supply Voltage  
3.135 3.3  
with Respect to GND  
V
SS  
Ground  
0
0
V
(3)  
TERM  
Terminal Voltage  
with Respect to GND  
-0.5 to VDD+0.5  
0 to +70  
V
____  
VIH  
VIH  
VIL  
Input High Voltage - Inputs  
Input High Voltage - I/O  
Input Low Voltage  
2.0  
4.6  
V
Commercial  
Operating Ambient  
Temperature  
2.0  
V
DD+0.3(2)  
0.8  
V
____  
____  
oC  
oC  
-0.5(1)  
V
T
A(4)  
Industrial  
Operating Ambient  
Temperature  
3821 tbl 04  
NOTES:  
-40 to +85  
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.  
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.  
3. VDD needs to be ramped up smoothly to the operating level. If there are any  
glitches on VDD that cause the voltage level to drop below 2.0 volts then the  
device needs to be reset by holding VDD to 0.0 volts for a minimum of 100 ms.  
T
BIAS  
Temperature Under Bias  
Storage Temperature  
Power Dissipation  
-55 to +125  
-55 to +125  
2.0  
oC  
oC  
W
TSTG  
P
T
I
OUT  
DC Output Current  
50  
mA  
RecommendedOperating  
TemperatureandSupplyVoltage  
Ambient  
3821 tbl 05  
NOTES:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS  
may cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions above  
those indicated in the operational sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may  
affect reliability.  
2. VDD and Input terminals only.  
3. I/O terminals.  
4. During production testing, the case temperature equals the ambient temperature.  
Grade  
Commercial  
Industrial  
Temperature(1)  
0OC to +70OC  
-40OC to +85OC  
V
SS  
VDD  
0V  
0V  
3.3V±5%  
3.3V±5%  
3821 tbl 03  
NOTES:  
1. During production testing, the case temperature equals the ambient temperature.  
100TQFPCapacitance  
(TA = +25°C, f = 1.0MHz, TQFP package)  
Symbol  
CIN  
Parameter(1 )  
Input Capacitance  
I/O Capacitance  
Conditions  
VIN = 3dV  
Max. Unit  
5
7
pF  
CI/O  
VOUT = 3dV  
pF  
3821 tbl 06  
NOTE:  
1. This parameter is guaranteed by device characterization, but not production tested.  
5
6.42  

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