Datasheet > 71V546XS117PFG

71V546XS117PFG

更新时间： 2024-02-21 13:53:13

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
21页	164K
描述
3.3V Synchronous SRAM

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技术参数
数据手册

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71V546XS117PFG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	QFP, QFP100,.63X.87
Reach Compliance Code：	compliant	风险等级：	5.56
最长访问时间：	4.5 ns	最大时钟频率 (fCLK)：	117 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e3	内存密度：	4718592 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	最大待机电流：	0.04 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.275 mA	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

71V546XS117PFG 数据手册

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT™ Feature, Burst Counter and Pipelined Outputs

Commercial and Industrial Temperature Ranges

PinDefinitions⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

Address Inputs

N/A

Synchronous Address inputs. The address register is triggered by a

combination of the rising edge of CLK and ADV/LD Low, CEN Low and true

chip enables.

A0 - A16

ADV/LD

Address/Load

N/A

ADV/LD is a synchronous input that is used to load the internal registers with

new address and control when it is sampled low at the rising edge of clock with

the chip selected. When ADV/LD is low with the chip deselected, any burst in

progress is terminated. When ADV/LD is sampled high then the internal burst

counter is advanced for any burst that was in progress. The external addresses

are ignored when ADV/LD is sampled high.

R/W

Read/Write

N/A

R/W signal is a synchronous input that identified whether the current load cycle

initiated is a Read or Write access to the memory array. The data bus activity for

the current cycle takes place two clock cycles later.

Clock Enable

LOW

Synchronous Clock Enable Input. When CEN is sampled high, all other

synchronous inputs, including clock are ignored and outputs remain unchanged.

The effect of CEN sampled high on the device outputs is as if the low to high

clock transition did not occur. For normal operation, CEN must be sampled low

at rising edge of clock.

CEN

Individual Byte

Write Enables

LOW

Synchronous byte write enables. Enable 9-bit byte has its own active low byte

- BW

write enable. On load write cycles (When R/W and ADV/LD are sampled low)

the appropriate byte write signal (BW

- BW4) must be valid. The byte write

signal must also be valid on each cycle of a burst write. Byte Write signals are

ignored when R/W is sampled high. The appropriate byte(s) of data are written

into the device two cycles later. BW

- BW

4 can all be tied low if always doing

write to the entire 36-bit word.

Chip Enables

Synchronous active low chip enable. CE

and CE

are used with CE

2 to

, CE

enable the IDT71V546. (CE or CE sampled high or CE

sampled low) and

ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT

has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after

deselect is initiated.

CE2

CLK

Chip Enable

Clock

HIGH

N/A

Synchronout active high chip enable. CE

is used with CE

and CE

2 to enable

the chip. CE has inverted polarity but otherwise identical to CE

and CE2.

This is the clock input to the IDT71V546. Except for OE, all timing references for

the device are made with respect to the rising edge of CLK.

I/O

- I/O31

Data Input/Output

I/O

N/A

Synchronous data input/output (I/O) pins. Both the data input path and data

output path are registered and triggered by the rising edge of CLK.

I/OP1 - I/OP4

Linear Burst

Order

LOW

Burst order selection input. When LBO is high the Interleaved burst sequence is

selected. When LBO is low the Linear burst sequence is selected. LBO is a

static DC input.

LBO

Output Enable

LOW

Asynchronous output enable. OE must be low to read data from the 71V546.

When OE is high the I/O pins are in a high-impedance state. OE does not need

to be actively controlled for read and write cycles. In normal operation, OE can

be tied low.

Power Supply

Ground

N/A

3.3V power supply input.

Ground pin.

3821 tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

123 4 5 6 7...21

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