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71V2558XSA133BGG PDF预览

71V2558XSA133BGG

更新时间: 2024-10-29 08:24:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
28页 567K
描述
ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, 22 X 14 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-119

71V2558XSA133BGG 数据手册

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IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs  
with 2.5V I/O, Burst Counter, and Pipelined Outputs  
Commercial and Industrial Temperature Ranges  
FunctionalBlockDiagram  
256x18 BIT  
MEMORY ARRAY  
LBO  
Address A [0:17]  
D
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
CEN  
Control  
ADV/LD  
BWx  
DI  
DO  
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Output Register  
Q
Clock  
Gate  
OE  
4875 drw 01b  
TMS  
TDI  
TCK  
Data I/O [0:15],  
I/O P[1:2]  
JTAG  
(SA Version)  
TDO  
TRST  
(optional)  
RecommendedDCOperating  
Conditions  
Symbol  
Parameter  
Core Supply Voltage  
I/O Supply Voltage  
Supply Voltage  
Min.  
3.135  
2.375  
0
Typ.  
Max.  
3.465  
2.625  
0
Unit  
V
V
DD  
DDQ  
SS  
IH  
IH  
IL  
3.3  
V
2.5  
V
V
0
V
____  
V
Input High Voltage - Inputs  
Input High Voltage - I/O  
Input Low Voltage  
1.7  
V
DD +0.3  
V
(2)  
____  
____  
V
1.7  
VDDQ +0.3  
V
V
-0.3(1)  
0.7  
V
4875 tbl 03  
NOTES:  
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.  
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.  
6.442  

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