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71V2558XSA133BGG PDF预览

71V2558XSA133BGG

更新时间: 2024-10-29 08:24:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
28页 567K
描述
ZBT SRAM, 256KX18, 4.2ns, CMOS, PBGA119, 22 X 14 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-119

71V2558XSA133BGG 数据手册

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IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs  
with 2.5V I/O, Burst Counter, and Pipelined Outputs  
Commercial and Industrial Temperature Ranges  
Pin Definitions(1)  
Symbol  
Pin Function  
I/O  
Active  
Description  
A0-A17  
Address Inputs  
I
N/A  
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of  
CLK, ADV/LD low, CEN low, and true chip enables.  
ADV/LD  
Advance / Load  
I
N/A  
N/A  
ADV/LD is a synchronous input that is used to load the internal registers with new address and control  
when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the  
chip deselected, any burstin progress is terminated. When ADV/LD is sampled high then the internal  
burst counter is advanced for any burst that was in progress. The external addresses are ignored  
when ADV/LD is sampled high.  
R/W  
Read / Write  
Clock Enable  
I
I
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or  
Write access to the memory array. The data bus activity for the current cycle takes place two clock  
cycles later.  
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including  
clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device  
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be  
sampled low at rising edge of clock.  
CEN  
Individual Byte  
Write Enables  
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load  
BW  
1
-BW  
4
write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW  
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write  
signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the  
device two cycles later. BW -BW can all be tied low if always doing write to the entire 36-bit word.  
1-BW4)  
1
4
Chip Enables  
LOW Synchronous active low chip enable. CE and CE are used with CE to enable the IDT71V2556/58.  
1
2
2
CE1  
, CE  
2
(CE  
1
or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a  
deselect cycle. The ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles  
after deselect is initiated.  
CE  
2
Chip Enable  
Clock  
I
I
HIGH Synchronous active high chip enable. CE  
2
is used with CE  
1
and CE2 to enable the chip. CE2 has  
inverted polarity but otherwise identical to CE  
1
and CE  
2.  
CLK  
N/A  
N/A  
This is the clock input to the IDT71V2556/58. Except for OE, all timing references for the device are  
made with respect to the rising edge of CLK.  
I/O0-I/O31  
Data Input/Output  
Linear Burst Order  
I/O  
I
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered  
and triggered by the rising edge of CLK.  
I/OP1-I/OP4  
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO  
is low the Linear burst sequence is selected. LBO is a static input and it must not change during  
device operation.  
LBO  
Output Enable  
I
LOW Asynchronous output enable. OE must be low to read data from the 71V2556/58. When OE is high the  
I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and write  
cycles. In normal operation, OE can be tied low.  
OE  
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal  
pullup.  
TMS  
TDI  
Test Mode Select  
Test Data Input  
Test Clock  
I
I
N/A  
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has  
an internal pullup.  
N/A  
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of  
TCK, while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.  
TCK  
TDO  
I
N/A  
Serial output of registers placed between TDI and TDO. This output is active depending on the state of  
the TAP controller.  
Test Data Output  
O
N/A  
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG  
LOW reset occurs automatically at power up and also resets using TMS and TCK p er IEEE 1149.1. If not  
used TRST can be left floating. This pin has an internal pullup.  
JTAG Reset  
(Optional)  
I
I
TRST  
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the  
HIGH IDT71V2556/2558 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.  
This pin has an internal pulldown  
ZZ  
Sleep Mode  
V
DD  
DDQ  
SS  
Power Supply  
Power Supply  
Ground  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
3.3V core power supply.  
2.5V I/O Supply.  
Ground.  
V
V
4875 tbl 02  
NOTE:  
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.  
6.422  

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