Datasheet > 70V7599S200BFG8

70V7599S200BFG8

更新时间： 2024-11-06 00:42:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	755K
描述
HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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70V7599S200BFG8 数据手册

HIGH-SPEED 3.3V 128K x 36

SYNCHRONOUS

IDT70V7599S

BANK-SWITCHABLE

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

Features:

◆

128K x 36 Synchronous Bank-Switchable Dual-ported

SRAM Architecture

– Data input, address, byte enable and control registers

– Self-timedwriteallowsfastcycletime

– 64 independent 2K x 36 banks

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

– 4 megabits of memory on chip

◆

Bank access controlled via bank address pins

High-speed data access

LVTTL- compatible, 3.3V (±150mV) power supply

for core

– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV)

power supply for I/Os and control signals on each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

◆

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

GridArray(BGA)

◆

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

◆

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

FunctionalBlockDiagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CE0R

CE1R

BE3R

BE2R

BE1R

BE0R

OPT

CLK

ADS

CNTEN

REPEAT

R/W

MUX

CE0L

CE1L

BE3L

BE2L

BE1L

BE0L

CONTROL

LOGIC

CONTROL

LOGIC

2Kx36

MEMORY

ARRAY

(BANK 0)

OEL

OER

MUX

I/O

CONTROL

I/O

CONTROL

I/O0L-35L

I/O0R-35R

2Kx36

MEMORY

ARRAY

10R

(BANK 1)

10L

ADDRESS

DECODE

ADDRESS

DECODE

MUX

BA5R

BA4R

BA3R

BA2R

BA1R

BA0R

BA5L

BA4L

BA3L

BA2L

BA1L

BA0L

BANK

DECODE

BANK

DECODE

MUX

2Kx36

MEMORY

ARRAY

(BANK 63)

MUX

NOTE:

1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.

As a result, it has unique operating characteristics.

Please refer to the functional description on page 19

for details.

5626 drw 01

TMS

TCK

TRST

TDI

TDO

JTAG

JUNE 2015

DSC 5626/7

12 3 4 5 6 7...22

中文翻译

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与70V7599S200BFG8相关器件

型号	品牌	获取价格	描述	数据表
70V7599S200BFGI	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7599S200BFGI8	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7599S200BFI	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
70V7599S200DR	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
70V7599S200DRG	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7599S200DRG8	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7599S200DRGI	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7599S200DRGI8	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7599S200DRI	IDT	获取价格	HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
70V9079	RENESAS	获取价格	32K x 8 Sync, 3.3V Dual-Port RAM, Pipelined/Flow-Through

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