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70V34S20PFGI8 PDF预览

70V34S20PFGI8

更新时间: 2024-09-20 20:52:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 725K
描述
Dual-Port SRAM

70V34S20PFGI8 技术参数

生命周期:Active包装说明:QFP,
Reach Compliance Code:compliantHTS代码:8542.32.00.41
风险等级:5.74最长访问时间:20 ns
JESD-30 代码:S-PQFP-G100内存密度:147456 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
功能数量:1端子数量:100
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX18
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子位置:QUADBase Number Matches:1

70V34S20PFGI8 数据手册

 浏览型号70V34S20PFGI8的Datasheet PDF文件第2页浏览型号70V34S20PFGI8的Datasheet PDF文件第3页浏览型号70V34S20PFGI8的Datasheet PDF文件第4页浏览型号70V34S20PFGI8的Datasheet PDF文件第5页浏览型号70V34S20PFGI8的Datasheet PDF文件第6页浏览型号70V34S20PFGI8的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
8/4K x 18 DUAL-PORT  
8/4K x 16 DUAL-PORT  
STATIC RAM  
IDT70V35/34S/L  
IDT70V25/24S/L  
Features  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
IDT70V35/34 (IDT70V25/24) easily expands data bus width  
to 36 bits (32 bits) or more using the Master/Slave select  
when cascading more than one device  
High-speed access  
IDT70V35/34  
– Commercial:15/20/25ns(max.)  
– Industrial:20ns  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
IDT70V25  
BUSY and Interrupt Flag  
– Commercial:15/20/25/35/55ns(max.)  
– Industrial:20/25ns  
IDT70V24  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
– Commercial:15/20/25/35/55ns(max.)  
– Industrial:20ns  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),  
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Low-power operation  
– IDT70V35/34S  
IDT70V35/34L  
Active: 430mW (typ.)  
Standby: 3.3mW (typ.)  
– IDT70V25/24S  
Active: 415mW (typ.)  
Standby: 660µW (typ.)  
IDT70V25/24L  
Green parts available, see ordering information  
Active: 400mW (typ.)  
Standby: 3.3mW (typ.)  
Active: 380mW (typ.)  
Standby: 660µW (typ.)  
Functional Block Diagram  
R/W  
L
R/W  
R
R
UBL  
UB  
LB  
CE  
OE  
R
R
R
LB  
CE  
OE  
L
L
L
,
(5)  
(5)  
I/O9R-I/O17R  
I/O9L-I/O17L  
I/O  
Control  
I/O  
Control  
(4)  
(4)  
I/O0R-I/O8R  
I/O0L-I/O8L  
(2,3)  
L
(2,3)  
BUSY  
R
BUSY  
(1)  
12R  
(1)  
12L  
A
A
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
A0R  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
R
CE  
OE  
R/W  
L
L
R
R
L
SEM  
R
SEM  
INTL  
L
(3)  
(3)  
INTR  
M/S  
NOTES:  
5624 drw 01  
1. A12 is a NC for IDT70V34 and for IDT70V24.  
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull.  
4. I/O0x - I/O7x for IDT70V25/24.  
5. I/O8x - I/O15x for IDT70V25/24.  
AUGUST 2015  
1
DSC-5624/8  
©2015 Integrated Device Technology, Inc.  

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