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70V27S55BF

更新时间: 2024-11-09 06:10:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
21页 178K
描述
Application Specific SRAM, 32KX16, 55ns, CMOS, PBGA144

70V27S55BF 数据手册

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HIGH-SPEED 3.3V  
32K x 16 DUAL-PORT  
STATIC RAM  
IDT70V27S/L  
Features:  
IDT70V27 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
– Commercial:15/20/25/35/55ns(max.)  
Industrial:20/35ns (max.)  
Low-power operation  
Busy and Interrupt Flags  
On-chip port arbitration logic  
IDT70V27S  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in 100-pin Thin Quad Flatpack (TQFP), and 144-  
pin Fine Pitch BGA (fpBGA)  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
Active:500mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V27L  
Active:500mW(typ.)  
Standby:660µW(typ.)  
Separate upper-byte and lower-byte control for bus  
matching capability  
Dual chip enables allow for depth expansion without  
external logic  
FunctionalBlockDiagram  
R/W  
L
R/WR  
UB  
L
UB  
R
CE0L  
CE0R  
CE1L  
CE1R  
OE  
R
OE  
L
L
LB  
R
LB  
I/O8-15L  
I/O0-7L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
,
(1,2)  
(1,2)  
BUSY  
L
BUSY  
R
32Kx16  
A
14R  
0R  
A
14L  
0L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
70V27  
A
A
A
14L  
A
A
CE0R  
14R  
0R  
A
CE0L  
0L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE1L  
CE1R  
OE  
OE  
L
R
R/  
WL  
R/WR  
L
L
SEM  
INT  
SEM  
R
(2)  
(2)  
INT  
R
M/S(2)  
NOTES:  
3603 drw 01  
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
OCTOBER 2008  
6.01  
1
DSC3603/11  
©2008IntegratedDeviceTechnology,Inc.  

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