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70V27S15PFGI PDF预览

70V27S15PFGI

更新时间: 2024-09-20 00:45:15
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 243K
描述
HIGH-SPEED 3.3V 32K x 16 DUAL-PORT STATIC RAM

70V27S15PFGI 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:QFP,Reach Compliance Code:compliant
风险等级:5.68最长访问时间:15 ns
JESD-30 代码:S-PQFP-G100内存密度:524288 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX16
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子位置:QUADBase Number Matches:1

70V27S15PFGI 数据手册

 浏览型号70V27S15PFGI的Datasheet PDF文件第2页浏览型号70V27S15PFGI的Datasheet PDF文件第3页浏览型号70V27S15PFGI的Datasheet PDF文件第4页浏览型号70V27S15PFGI的Datasheet PDF文件第5页浏览型号70V27S15PFGI的Datasheet PDF文件第6页浏览型号70V27S15PFGI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
32K x 16 DUAL-PORT  
STATIC RAM  
IDT70V27S/L  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Features:  
Dual chip enables allow for depth expansion without  
externallogic  
IDT70V27 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V ( 0.3V) power supply  
Available in 100-pin Thin Quad Flatpack (TQFP)  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
– Commercial:15/20/25/35/55ns(max.)  
– Industrial:15/20/35ns(max.)  
Low-power operation  
– IDT70V27S  
Active:500mW(typ.)  
Standby: 3.3mW (typ.)  
– IDT70V27L  
Active:500mW(typ.)  
Standby: 660µW(typ.)  
Separate upper-byte and lower-byte control for bus  
matchingcapability  
On-chip port arbitration logic  
Green parts available, see ordering information  
Functional Block Diagram  
R/  
W
L
R/W  
UB  
R
UB  
L
R
CE0L  
CE0R  
CE1L  
CE1R  
OE  
LB  
R
OE  
LB  
L
R
L
I/O8-15L  
I/O0-7L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
,
(1,2)  
(1,2)  
R
BUSY  
L
BUSY  
32Kx16  
A
A
14R  
0R  
A
14L  
0L  
Address  
Decoder  
Address  
Decoder  
MEMORY  
ARRAY  
70V27  
A
A
14L  
A
A
14R  
0R  
A
0L  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE0L  
CE1L  
CE1R  
OE  
R/  
L
L
OE  
R
W
R/  
W
R
L
L
SEM  
INT  
SEM  
R
(2)  
(2)  
INT  
R
M/S(2)  
NOTES:  
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).  
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
3603 drw 01  
JULY 2018  
6.01  
1
2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
©
DSC 3603/16  

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