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70V09L15PFGI8 PDF预览

70V09L15PFGI8

更新时间: 2024-11-24 19:43:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 152K
描述
Multi-Port SRAM, 128KX8, 15ns, CMOS, PQFP100

70V09L15PFGI8 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:QFP, QFP100,.63SQ,20Reach Compliance Code:compliant
风险等级:5.28最长访问时间:15 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
内存密度:1048576 bit内存集成电路类型:MULTI-PORT SRAM
内存宽度:8端口数量:2
端子数量:100字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
最小待机电流:3 V子类别:SRAMs
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

70V09L15PFGI8 数据手册

 浏览型号70V09L15PFGI8的Datasheet PDF文件第2页浏览型号70V09L15PFGI8的Datasheet PDF文件第3页浏览型号70V09L15PFGI8的Datasheet PDF文件第4页浏览型号70V09L15PFGI8的Datasheet PDF文件第5页浏览型号70V09L15PFGI8的Datasheet PDF文件第6页浏览型号70V09L15PFGI8的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
128K x 8 DUAL-PORT  
STATIC RAM  
IDT70V09L  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in a 100-pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
– Commercial: 15/20ns (max.)  
– Industrial: 20ns (max.)  
Low-power operation  
– IDT70V09L  
Active: 440mW (typ.)  
Standby: 660µW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT70V09 easily expands data bus width to 16 bits or  
more using the Master/Slave select when cascading more  
than one device  
Green parts available, see ordering information  
Functional Block Diagram  
R/WL  
CE0L  
CE1L  
R/WR  
CE0  
R
CE1R  
OEL  
OER  
I/O  
Control  
I/O  
Control  
0-7L  
I/O  
0-7R  
I/O  
(1,2)  
(1,2)  
R
BUSY  
L
BUSY  
128Kx8  
MEMORY  
ARRAY  
70V09  
16R  
A
16L  
A
Address  
Decoder  
Address  
Decoder  
A
0L  
0R  
A
17  
17  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE 0L  
CE1L  
CE0R  
CE1R  
OER  
OE  
L
R/WL  
R/W  
R
SEM  
INT  
L
L
SEM  
R
(2)  
(2)  
INT  
R
M/S(1)  
4852 drw 01  
NOTES:  
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
FEBRUARY 2013  
1
DSC-4852/6  
©2013IntegratedDeviceTechnology,Inc.  

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