Datasheet > 70V09LL20PFGI

70V09LL20PFGI

更新时间： 2024-11-05 19:43:07

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器内存集成电路
页数	文件大小	规格书
17页	152K
描述
Dual-Port SRAM

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中文翻译

获取价格

技术参数
数据手册

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70V09LL20PFGI 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.76	内存集成电路类型：	DUAL-PORT SRAM
Base Number Matches：	1

70V09LL20PFGI 数据手册

HIGH-SPEED 3.3V

128K x 8 DUAL-PORT

STATIC RAM

IDT70V09L

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

Low-power operation

◆

– IDT70V09L

Active: 440mW (typ.)

Standby: 660µW (typ.)

Dual chip enables allow for depth expansion without

external logic

IDT70V09 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading more

than one device

◆

Green parts available, see ordering information

Functional Block Diagram

R/W_L

CE0L

CE1L

R/W_R

CE0

CE1R

OE_L

OE_R

I/O

Control

I/O

Control

0-7L

I/O

0-7R

I/O

(1,2)

BUSY

128Kx8

MEMORY

ARRAY

70V09

16R

16L

Address

Decoder

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE _0L

CE_1L

CE_0R

CE_1R

OE_R

R/W_L

R/W

SEM

INT

SEM

(2)

INT

M/S⁽¹⁾

4852 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

FEBRUARY 2013

DSC-4852/6

12 3 4 5 6 7...17

中文翻译

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