Datasheet > 70V08S15PFG8

70V08S15PFG8

更新时间： 2024-11-06 00:41:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
21页	662K
描述
HIGH-SPEED 3.3V 64K x 8 DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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70V08S15PFG8 数据手册

IDT70V08S/L

HIGH-SPEED 3.3V

64K x 8 DUAL-PORT

STATIC RAM

Features

◆

IDT70V08 easily expands data bus width to 16 bits or

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

more using the Master/Slave select when cascading more

than one device

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

– Commercial:15/20/25/35ns(max.)

– Industrial: 20ns (max.)

◆

Busy and Interrupt Flags

Low-power operation

On-chip port arbitration logic

– IDT70V08S

Full on-chip hardware support of semaphore signaling

between ports

Active: 550mW (typ.)

Standby: 5mW (typ.)

◆

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in a 100-pin TQFP

– IDT70V08L

Active: 550mW (typ.)

Standby: 1mW (typ.)

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Dual chip enables allow for depth expansion without

external logic

◆

Green parts available, see ordering information

Functional Block Diagram

R/W_L

CE0L

CE1L

R/W_R

CE0

CE1R

OE_L

OE_R

I/O

Control

I/O

Control

0-7L

I/O

0-7R

I/O

(1,2)

BUSY

64Kx8

MEMORY

ARRAY

70V08

15L

15R

Address

Decoder

Address

Decoder

A_15L

A_15R

A_0L

CE _0L

CE_1L

A_0R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE_0R

CE_1R

OE_R

OE_L

R/W_L

R/W_R

SEM

INT

SEM

(2)

INT

M/S⁽¹⁾

3740 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S-VIL) and an output when it is a Master (M/S-VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

FEBRUARY 2015

DSC-3740/9

12 3 4 5 6 7...21

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