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70T3719MS166BBGI8 PDF预览

70T3719MS166BBGI8

更新时间: 2024-09-19 00:53:47
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
25页 345K
描述
HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM

70T3719MS166BBGI8 数据手册

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HIGH-SPEED 2.5V  
256/128K x 72  
SYNCHRONOUS  
IDT70T3719/99M  
DUAL-PORTSTATICRAM  
WITH 3.3V OR 2.5V INTERFACE  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Features:  
True Dual-Port memory cells which allow simultaneous  
– 1.7ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 166MHz  
– Data input, address, byte enable and control registers  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
Dual Cycle Deselect (DCD) for Pipelined Output Mode  
2.5V ( 100mV) power supply for core  
LVTTL compatible, selectable 3.3V ( 150mV) or 2.5V  
( 100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 133MHz  
Available in a 324-pin Green Ball Grid Array (BGA)  
Includes JTAG Functionality  
Green parts available, see ordering information  
access of the same memory location  
High-speed data access  
– Commercial: 3.6ns (166MHz)/  
4.2ns (133MHz)(max.)  
– Industrial: 4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Interrupt and Collision Detection Flags  
Full synchronous operation on both ports  
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)  
– Fast 3.6ns clock to data out  
– Self-timedwriteallowsfastcycletime  
Functional Block Diagram  
BE7L  
BE7R  
BE0L  
BE0R  
FT/PIPE  
L
0a 1a  
a
0h 1h  
h
1h 0h  
h
1a 0a  
a
FT/PIPER  
1/0  
1/0  
R/WL  
R/WR  
CE0L  
CE0R  
1
1
CE1R  
CE1L  
0
0
B
W
0
B
W
7
B
W
7
B
W
0
1/0  
1/0  
L
L
R
R
OE  
R
OE  
L
D
D
D
D
D
D
D
D
OUT0-8_L  
OUT9-17_L  
D
D
D
D
D
D
D
D
OUT0-8_R  
OUT9-17_R  
OUT18-26_L  
OUT27-35_L  
OUT36-44_L  
OUT45-53_L  
OUT54-62_L  
OUT63-72_L  
OUT18-26_R  
OUT27-35_R  
OUT36-44_R  
OUT45-53_R  
OUT54-62_R  
OUT63-72_R  
,
1h 0h  
1a 0a  
0a 1a  
0h 1h  
0/1  
0/1  
FT/PIPER  
FT/PIPE  
L
a
h
h
a
256/128K x 72  
MEMORY  
ARRAY  
Byte 0  
I/O0L - I/O71L  
Byte 7  
Byte 7  
Byte 0  
I/O0R - I/O71R  
D
IN_L  
D
IN_R  
,
CLK  
L
CLKR  
(1)  
17L  
(1)  
17R  
A
A
A
A
0L  
REPEAT  
ADS  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
R
0
ADDR_R  
ADDR_L  
L
REPEAT  
ADS  
CNTEN  
R
R
L
R
CNTEN  
L
INTERRUPT  
CE  
0
L
CE0R  
TDI  
TDO  
TCK  
TMS  
T RST  
COLLISION  
DETECTION  
LOGIC  
CE  
1
L
CE1R  
JTAG  
R/W  
L
R/W  
R
L
COL  
INT  
R
COL  
INT  
L
R
ZZ  
CONTROL  
LOGIC  
(2)  
(2)  
ZZR  
ZZ  
L
5687 drw 01  
NOTES:  
1. Address A17 is a NC for the IDT70T3799.  
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx  
FEBRUARY 2018  
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.  
1
DSC 5687/4  
©2018 Integrated Device Technology, Inc.  

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