78P2352 Dual Channel OC-3/STM1-E/E4 Line Interface Unit
SERIAL CONTROL INTERFACE
FUNCTIONAL DESCRIPTION (continued)
The serial port controlled register allows a generic
controller to interface with the 78P2352. It is used
for mode settings, diagnostics and test, retrieval of
status and performance information, and for on-chip
trimming. The SPSL pin must be high in order to
use the serial port.
LOOPBACK MODES
In SW mode, LLBKx and RLBKx bits are provided to
activate the local and remote loopback modes
respectively. In HW mode, the LPBKx pins can be
used to activate local and remote loopback modes
as shown below.
The serial interface consists of four pins: Serial Port
Enable (SEN_CMI), Serial Clock (SCK_MON), Serial
Data In (SDI_PAR), and Serial Data Out (SDO_E4).
The SEN_CMI pin initiates the read and write
operations. It can also be used to select a particular
device allowing SCK_MON, SDI_PAR and SDO_E4
to be bussed together. SCK_MON is the clock input
that times the data on SDI_PAR and SDO_E4. Data
on SDI_PAR is latched in on the rising-edge of
SCK_MON, and data on SDO_E4 is clocked out
using the falling edge of SCK_MON.
SDI_PAR is used to insert mode, address, and
register data into the chip. Address and Data
information are input least significant bit (LSB) first.
The mode and address bit assignment and register
table are shown in the following section.
SDO_E4 is a tristate capable output. It is used to
output register data during a read operation.
SDO_E4 output is normally high impedance, and is
enabled only during the duration when register data
is being clocked out. Read data is clocked out least
significant bit (LSB) first.
If SDI_PAR coming out of the micro-controller chip is
also tristate capable, SDI_PAR and SDO_E4 can be
connected together to simplify connections.
LPBK pin Loopback Mode
Low
Normal operation
Remote (digital) Loopback:
Recovered receive clock and data
looped back to transmitter
Float
Local (analog) Loopback:
Transmit clock and data looped back to
receiver
High
EACH CHANNEL: Tx
Lock Detect
Tx CDR
ECLxP/N
SIxDP/N
TXxCKP/N
FIFO
CMI
Encoder
SIxCKP/N
CMIxP/N
PIxCK
PIx[3:0]D
PTOxCK
PMOD, SMOD[1:0], PAR
RLBK
SOxCKP/N
SOxDP/N
CMI
Rx CDR
Decoder
Adaptive
Eq.
RXxP/N
POx[3:0]D
POxCK
Lock Detect
LOS Detect
CMI
LLBK
EACH CHANNEL: Rx
Figure 6: Local (Analog) Loopback
EACH CHANNEL: Tx
Lock Detect
ECLxP/N
Tx CDR
SIxDP/N
TXxCKP/N
FIFO
CMI
Encoder
SIxCKP/N
CMIxP/N
PIxCK
PIx[3:0]D
PTOxCK
PMOD, SMOD[1:0], PAR
RLBK
SOxCKP/N
SOxDP/N
The maximum clock frequency for register access is
20MHz.
PROGRAMMABLE INTERRUPTS
CMI
Rx CDR
Decoder
Adaptive
Eq.
RXxP/N
POx[3:0]D
POxCK
Lock Detect
LOS Detect
CMI
LLBK
EACH CHANNEL: Rx
In addition to the receiver LOS and LOL status pins,
the 78P2352 provides a programmable interrupt for
each transmitter. In HW control mode, the default
functions of the Tx interrupt is a transmit Loss of
Lock (TXLOL) or FIFO error (FERR).
Figure 7: Remote (Digital) Loopback
INTERNAL POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Roughly 50us after Vcc reaches 2.4V at power up, a
reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin. The PORB pin is a special function pin
that allows for the following:
•
•
•
Override the internal POR signal by driving in
an external active low reset signal;
Use the POR signal to drive other IC’s power-
on reset;
Add external capacitor to slow down the
release of power-on reset (approximately 8µs
per nF added).
7
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