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7007S55JG PDF预览

7007S55JG

更新时间: 2024-10-26 14:40:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 176K
描述
Dual-Port SRAM, 32KX8, 55ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68

7007S55JG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ, PGA68,11X11针数:68
Reach Compliance Code:compliantECCN代码:3A991
HTS代码:8542.32.00.41风险等级:5.24
Is Samacsys:N最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J68
JESD-609代码:e3长度:24.2062 mm
内存密度:262144 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:1
功能数量:1端口数量:2
端子数量:68字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:PGA68,11X11封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:4.572 mm
最大待机电流:0.015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.27 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:24.2062 mm
Base Number Matches:1

7007S55JG 数据手册

 浏览型号7007S55JG的Datasheet PDF文件第2页浏览型号7007S55JG的Datasheet PDF文件第3页浏览型号7007S55JG的Datasheet PDF文件第4页浏览型号7007S55JG的Datasheet PDF文件第5页浏览型号7007S55JG的Datasheet PDF文件第6页浏览型号7007S55JG的Datasheet PDF文件第7页 
HIGH-SPEED  
32K x 8 DUAL-PORT  
STATIC RAM  
IDT7007S/L  
Features  
using the Master/Slave select when cascading more than  
one device  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
Military:25/35/55ns(max.)  
Industrial:20/25/35/55ns(max.)  
– Commercial:15/20/25/35/55ns(max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT7007S  
Fully asynchronous operation from either port  
TTL-compatible, single 5V (±10%) power supply  
Available in 68-pin PGA and PLCC and a 80-pin TQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Active:850mW(typ.)  
Standby: 5mW (typ.)  
IDT7007L  
Active:850mW(typ.)  
Standby: 1mW (typ.)  
IDT7007 easily expands data bus width to 16 bits or more  
Green parts available, see ordering information  
FunctionalBlockDiagram  
OER  
OEL  
CEL  
CER  
R/WR  
R/W  
L
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
(1,2)  
BUSY (1,2)  
L
BUSY  
R
A
14R  
0R  
A
14L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
15  
15  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
L
L
CE  
OE  
R/W  
R
OE  
R
R
R/W  
L
SEM  
R
SEM (2)  
L
M/S  
(2)  
INT  
R
INT  
L
2940 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY and INT outputs are non-tri-stated push-pull.  
OCTOBER 2008  
1
©2008IntegratedDeviceTechnology,Inc.  
DSC 2940/13  

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