HIGH-SPEED
64K x 8 DUAL-PORT
7008S/L
STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
– Commercial:15/25/35/55ns(max.)
– Industrial: 20ns (max.)
Low-poweroperation
◆
◆
◆
◆
– IDT7008S
Active:750mW(typ.)
Standby: 5mW (typ.)
– IDT7008L
◆
◆
◆
◆
Active:750mW(typ.)
Standby: 1mW (typ.)
◆
Dual chip enables allow for depth expansion without
external logic
◆
Green parts available, see ordering information
FunctionalBlockDiagram
R/W
L
R
R/W
CE0L
CE1L
CE0R
CE1R
OE
L
OE
R
I/O
Control
I/O
Control
I/O0-7L
I/O0-7R
BUSYL(1,2)
(1,2)
BUSY
R
64Kx8
MEMORY
ARRAY
7008
A
15L
A
A
15R
0R
Address
Decoder
Address
Decoder
A
0L
16
16
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE0L
CE0R
1L
CE
1R
CE
OE
L
L
OE
R
R/W
R
R/W
SEM
INTL
L
R
SEM
(2)
(2)
INT
R
M/S(1)
3198 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
1
Jan.05.22