Datasheet > 存储 > SRAM> 7005S55PFGB

7005S55PFGB

更新时间： 2024-01-28 20:14:39

品牌	Logo	应用领域
艾迪悌 - IDT		存储内存集成电路静态存储器
页数	文件大小	规格书
21页	363K
描述
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

7005S55PFGB 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	QFP, QFP64,.66SQ,32	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.05
Is Samacsys：	N	最长访问时间：	55 ns
I/O 类型：	COMMON	JESD-30 代码：	S-PQFP-G64
JESD-609代码：	e3	内存密度：	65536 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	8
湿度敏感等级：	3	功能数量：	1
端口数量：	2	端子数量：	64
字数：	8192 words	字数代码：	8000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	8KX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP64,.66SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	5 V	认证状态：	Not Qualified
最大待机电流：	0.03 A	最小待机电流：	4.5 V
子类别：	SRAMs	最大压摆率：	0.3 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	Base Number Matches：	1

7005S55PFGB 数据手册

IDT7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

SLAVE

Dual Port

RAM

MASTER

Dual Port

RAM

BUSY (L) BUSY (R)

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

BUSY (R)

BUSY (L) BUSY (R)

BUSY (L)

2738 drw 19

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.

BusyLogic

address signals only. It ignores whether an access is a read or write.

In a master/slave array, both address and chip enable must be valid

long enough for a BUSY flag to be output from the master before the

actualwritepulsecanbeinitiatedwiththeR/Wsignal.Failuretoobserve

thistimingcanresultinaglitchedinternalwriteinhibitsignalandcorrupted

dataintheslave.

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.

The BUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

TheBUSYoutputsontheIDT7005RAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

Semaphores

TheIDT7005isanextremelyfastDual-Port8Kx8CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completelyindependentofeachother.Thismeansthattheactivityonthe

leftportinnowayslowstheaccesstimeoftherightport. Bothportsare

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chip power down circuitry that permits the respective port to go into

standbymodewhennotselected. Thisistheconditionwhichisshownin

Truth Table I where CE and SEM are both HIGH.

SystemswhichcanbestusetheIDT7005containmultipleprocessors

or controllers and are typically very high-speed systems which are

softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom

aperformanceincreaseofferedbytheIDT7005'shardwaresemaphores,

whichprovidealockoutmechanismwithoutrequiringcomplexprogram-

ming.

Width Expansion with Busy Logic

Master/SlaveArrays

WhenexpandinganIDT7005RAMarrayinwidthwhileusingBUSY

logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill

receivea BUSYindication,andtooutputthatindication.Anynumberof

slavestobeaddressedinthesameaddressrangeasthemaster,usethe

BUSYsignalasawriteinhibitsignal.ThusontheIDT7005RAMtheBUSY

pinisanoutputifthepartisusedasamaster(M/Spin=VIH),andtheBUSY

pin is an input if the part used as a slave (M/S pin = VIL) as shown in

Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSY ononesideofthe

arrayandanothermasterindicating BUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

The BUSY arbitration on a master is based on the chip enable and

Softwarehandshakingbetweenprocessorsoffersthemaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

6.42

1...14 15 161718 19 20 21

下载PDF

与7005S55PFGB相关器件

型号	品牌	描述	获取价格	数据表
7005S55PFGB8	IDT	Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64	获取价格
7005S55PFGI	IDT	Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64	获取价格
7005S55PFGI8	IDT	Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64	获取价格
7005S70FGB	IDT	Dual-Port SRAM, 8KX8, 70ns, CMOS, PQFP68, 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, GREEN, QF	获取价格
7005S70FGB8	IDT	Dual-Port SRAM, 8KX8, 70ns, CMOS, PQFP68, 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, GREEN, QF	获取价格
7005S70GG	IDT	HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM	获取价格

与7005S55PFGB相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

17
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

16
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

14
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

11

产品中心

服务支持

精选活动

关于我们

帮助中心

7005S55PFGB

7005S55PFGB 技术参数

7005S55PFGB 数据手册

与7005S55PFGB相关器件

与7005S55PFGB相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

7005S55PFGB

7005S55PFGB 技术参数

7005S55PFGB 数据手册

与7005S55PFGB相关器件

与7005S55PFGB相关文章

您还可以找

您在本页遇到什么问题？