HIGH-SPEED
IDT7005S/L
8K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Interrupt Flag
◆
◆
◆
◆
– Military:20/25/35/55/70ns(max.)
– Industrial:20/35/55ns(max.)
– Commercial:15/17/20/25/35/55ns(max.)
Low-power operation
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
◆
◆
◆
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
– IDT7005S
Active:750mW(typ.)
◆
◆
◆
Standby: 5mW (typ.)
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, PLCC and a 64-pin thin quad
flatpack
– IDT7005L
Active:700mW(typ.)
Standby: 1mW (typ.)
◆
◆
◆
IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
Industrial temperature range (-40°C to +85°C) is available for
selectedspeeds
Green parts available, see ordering information
FunctionalBlockDiagram
OER
OEL
CEL
CER
R/W
L
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
I/O
Control
Control
BUSY (1,2)
L
(1,2)
BUSY
R
A
12R
0R
A
12L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
L
L
CE
OE
R/W
R
R
R
R/W
L
SEM
R
SEM
L
M/S
(2)
(2)
INTR
INTL
2738 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
JUNE 2016
1
DSC 2738/18
©2016 Integrated Device Technology, Inc.