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7005S55PFGB PDF预览

7005S55PFGB

更新时间: 2024-01-09 15:28:05
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器
页数 文件大小 规格书
21页 363K
描述
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64

7005S55PFGB 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:QFP, QFP64,.66SQ,32针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.05
Is Samacsys:N最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G64
JESD-609代码:e3内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端口数量:2端子数量:64
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:8KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
最大待机电流:0.03 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30Base Number Matches:1

7005S55PFGB 数据手册

 浏览型号7005S55PFGB的Datasheet PDF文件第12页浏览型号7005S55PFGB的Datasheet PDF文件第13页浏览型号7005S55PFGB的Datasheet PDF文件第14页浏览型号7005S55PFGB的Datasheet PDF文件第16页浏览型号7005S55PFGB的Datasheet PDF文件第17页浏览型号7005S55PFGB的Datasheet PDF文件第18页 
IDT7005S/L  
High-Speed 8K x 8 Dual-Port Static RAM  
Military, Industrial and Commercial Temperature Ranges  
Waveform of Interrupt Timing(1)  
tWC  
ADDR"A"  
INTERRUPT SET ADDRESS(2)  
(3)  
AS  
(4)  
t
tWR  
CE"A"  
R/W"A"  
INT"B"  
(3)  
INS  
t
2738 drw 17  
t
RC  
INTERRUPT CLEAR ADDRESS(2)  
ADDR"B"  
CE"B"  
(3)  
AS  
t
OE"B"  
(3)  
INR  
t
INT"B"  
2738 drw 18  
NOTES:  
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.  
2. See Interrupt Truth Table III.  
3. Timing depends on which enable signal (CE or R/W) asserted last.  
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.  
Truth Table III — Interrupt Flag(1,4)  
Left Port  
Right Port  
R/W  
L
A
12L-A0L  
1FFF  
X
R/W  
R
A
12R-A0R  
Function  
Set Right INT Flag  
Reset Right INT Flag  
Set Left INT Flag  
Reset Left INT Flag  
CE  
L
OE  
L
INT  
L
CE  
R
OE  
R
INTR  
L
X
X
X
L
X
X
L
X
X
X
X
X
L
X
L
X
L(2)  
H(3)  
X
R
X
X
1FFF  
1FFE  
X
R
X
X
L(3)  
H(2)  
L
L
X
X
L
L
1FFE  
X
X
X
L
2738 tbl 17  
NOTES:  
1. Assumes BUSYL = BUSYR = VIH.  
2. If BUSYL = VIL, then no change.  
3. If BUSYR = VIL, then no change.  
4. INTR and INTL must be initialized at power-up.  
6.42  
15  

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