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5V9885TNLGI8

更新时间： 2024-01-08 09:13:29
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
39页 513K
描述
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

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5V9885TNLGI8 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：VFQFPN
包装说明：QCCN, LCC28,.24SQ,25针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.29
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/730035.2.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=730035
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=7300353D View：https://componentsearchengine.com/viewer/3D.php?partID=730035
Samacsys PartID：730035Samacsys Image：https://componentsearchengine.com/Images/9/5V9885TNLGI8.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/2/5V9885TNLGI8.jpgSamacsys Pin Count：29
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Quad Flat No-Lead
Samacsys Footprint Name：nlg28Samacsys Released Date：2020-01-16 10:43:20
Is Samacsys：NJESD-30 代码：S-XQCC-N28
JESD-609代码：e3长度：6.3 mm
湿度敏感等级：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：500 MHz封装主体材料：UNSPECIFIED
封装代码：QCCN封装等效代码：LCC28,.24SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：400 MHz认证状态：Not Qualified
子类别：Clock Generators最大压摆率：110 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.3 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

5V9885TNLGI8 数据手册

 浏览型号5V9885TNLGI8的Datasheet PDF文件第5页浏览型号5V9885TNLGI8的Datasheet PDF文件第6页浏览型号5V9885TNLGI8的Datasheet PDF文件第7页浏览型号5V9885TNLGI8的Datasheet PDF文件第9页浏览型号5V9885TNLGI8的Datasheet PDF文件第10页浏览型号5V9885TNLGI8的Datasheet PDF文件第11页 
IDT5V9885T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
Notethattheactual10-bitpost-dividervaluehasa2addedtotheintegervalueQandtheoutputsareroutedthroughanotherdiv/2block. Thepost-divider  
shouldneverbedisabledunlesstheoutputbankwillneverbeusedduringnormaloperation. TheoutputfrequencyrangeforLVTTLoutputsarefrom4.9KHz  
to 200MHz. The output frequency range for LVPECL/LVDS outputs are from 4.9KHz to 500MHz.  
SPREADSPECTRUMGENERATION  
PLL0andPLL1supportspreadspectrumgenerationcapability,whichusershavetheoptionofturningonandoff. Spreadspectrumprofile,frequency,and  
spreadarefullyprogrammable(withinlimits). TheprogrammablespreadspectrumgenerationparametersareTSSC[3:0], NSSC[3:0], SS_OFFSET[5:0],  
SD[3:0],DITH,andX2bits. Thesebitsareinthememoryaddressrangeof0x60to0x67forPLL0and0x68to0x6FforPLL1. Thespreadspectrumgeneration  
on PLL0 & PLL1 can be enabled/disabled using the TSSC[3:0] bits. To enable spread spectrum, set TSSC > '0' and set NSSC, SD[3:0], SD[5:0], and the  
A[3:0] in the total M value accordingly. And to disable, set TSSC = '0'.  
TSSC[3:0]  
Thesebitsareusedtodeterminethenumberofphase/frequencydetectorcyclesperspreadspectrumcycle(ssc)steps. Themodulationfrequencycanbe  
calculatedwiththeTSSCbitsinconjunctionwiththeNSSCbits. ValidTSSCintegervaluesforthemodulationfrequencyrangefrom5to14.  
NSSC[3:0]  
Thesebitsareusedtodeterminethenumberofdelta-encodedsamplesusedforasinglequadrantof thespreadspectrumwaveform. Allfourquadrants  
ofthespreadspectrumwaveformaremirrorimagesofeachother. ThemodulationfrequencyisalsocalculatedbasedofftheNSSCbitsinconjunctionwiththe  
TSSC bits. Valid NSSC integer values range from 1 to 6.  
SS_OFFSET[5:0]  
ThesebitsareusedtoprogramthefractionaloffsetwithrespecttothenominalMintegervalue. Forcenterspread,theSS_OFFSETshouldbesetto'0'so  
thespreadspectrumwaveformisaboutthenominalM(Mnom)value. Fordownspread,theSS_OFFSET>'0'sothespreadspectrumwavformisaboutthe  
(Mideal-1=Mnom)value. Thedownspreadpercentagecanbethoughtofintermsofcenterspread. Forexample,adownspreadof-1%canalsobeconsidered  
as a center spread of ±0.5% but with Mnom shifted down by one and offset. The SS_OFFSET has integer values ranging from 0 to 63.  
SD[3:0]  
Thesebitsareusedtoshapetheprofileofthespreadspectrumwaveform. Thesearedelta-encodedsamplesofthewaveform. Therearetwelvesetsof  
SDsamplesforeachPLL. TheNSSCbitsdeterminehowmanyofthesesamplesareusedforthewaveform. Thesumofthesedelta-encodedsamples(sigma-  
delta-encodedsamples)determinetheamountofspreadandshouldnotexceed(63-SS_OFFSET). Themaximumspreadisinverselyproportionaltothe  
nominalMintegervalue.  
DITH  
Thisbitisforditheringthesigma-delta-encodedsamples. Thiswillrandomizetheleast-significantbitoftheinputtothespreadspectrummodulator. Setthe  
bitto'1'toenabledithering.  
X2  
Thisbitwilldoublethetotalvalueofthesigma-delta-encoded-sampleswhichwillincreasetheamplitudeofthespreadspectrumwaveformbyafactoroftwo.  
WhenX2is'0', theamplituderemainsnominalbutifsetto'1', theamplitudeisincreasedbyx2.  
Thefollowingequationsgovernhowthespreadspectrumisset:  
TSSC = TSSC[3:0] + 2 (Eq. 7)  
NSSC = NSSC[3:0] * 2 (Eq. 8)  
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 9)  
where SJ is the unencoded sample out of a possible 12 and SDK is the delta-encoded sample out of a possible 12.  
Amplitude = (2*N[11:0] + A[3:0] + 1) * Spread% / 100  
(Eq. 10)  
2
if 1 < Amp < 2, then set X2 bit to '1'.  
8
1...567891011...39

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