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5V9885TNLGI8

更新时间： 2024-01-24 10:27:26
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
39页 513K
描述
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

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5V9885TNLGI8 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：VFQFPN
包装说明：QCCN, LCC28,.24SQ,25针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.29
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/730035.2.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=730035
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=7300353D View：https://componentsearchengine.com/viewer/3D.php?partID=730035
Samacsys PartID：730035Samacsys Image：https://componentsearchengine.com/Images/9/5V9885TNLGI8.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/2/5V9885TNLGI8.jpgSamacsys Pin Count：29
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Quad Flat No-Lead
Samacsys Footprint Name：nlg28Samacsys Released Date：2020-01-16 10:43:20
Is Samacsys：NJESD-30 代码：S-XQCC-N28
JESD-609代码：e3长度：6.3 mm
湿度敏感等级：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：500 MHz封装主体材料：UNSPECIFIED
封装代码：QCCN封装等效代码：LCC28,.24SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：400 MHz认证状态：Not Qualified
子类别：Clock Generators最大压摆率：110 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.3 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

5V9885TNLGI8 数据手册

 浏览型号5V9885TNLGI8的Datasheet PDF文件第4页浏览型号5V9885TNLGI8的Datasheet PDF文件第5页浏览型号5V9885TNLGI8的Datasheet PDF文件第6页浏览型号5V9885TNLGI8的Datasheet PDF文件第8页浏览型号5V9885TNLGI8的Datasheet PDF文件第9页浏览型号5V9885TNLGI8的Datasheet PDF文件第10页 
IDT5V9885T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
Feedback-Divider  
N[11:0]andA[3:0]arethebitsusedtoprogramthefeedback-dividerforPLL0(N0andA0)andPLL1(N1andA1). Ifspreadspectrumgenerationisenabled  
foreitherPLL0orPLL1,thenthe SS_OFFSET[5:0]bits(0x61,0x69)wouldbefactoredintotheoverallfeedbackdividervalue. SeetheSPREADSPECTRUM  
GENERATIONsectionformoredetailsonhowtoconfigurePLL0andPLL1whenspreadspectrumisenabled. ThetwoPLLscanalsobeconfiguredforfractional  
divideratios. SeeFRACTIONALDIVIDERformoredetails. ForPLL2,onlytheN[11:0]bits(N2)areusedtoprogramitsfeedbackdividerandthereisnospread  
spectrumgenerationandfractionaldividescapability. The12-bitfeedback-dividerintegervaluesrangefrom1to4095.  
The following equations govern how the feedback divider value is set. Note that the equations are different for PLL0/PLL1 and PLL2  
PLL0 and PLL1:  
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] * 1/64  
M = 2*N[11:0] + A[3:0] + 1 (spread spectrum disabled)  
(Eq. 3)  
(Eq. 4)  
A[3:0] = 0000 = -1  
= 0001 = 1  
= 0010 = 2  
= 0011 = 3  
.
.
.
= 1111 = 15  
Note: A[3:0] < (N[11:0] - 5), must be met when using A. N cannot be programmed with a value of 4, 8, or 16 when using A.  
PLL2:  
M = N[11:0]  
(Eq. 5)  
TheusercanachieveanevenoroddintegerdivideratioforbothPLL0andPLL1bysettingtheA[3:0]bitsaccordinglyanddisablingthespreadspectrum.  
AfractionaldividecanalsobesetforPLL0andPLL1byusingtheA[3:0]bitsinconjunctionwiththeSS_OFFSET[5:0]bits,whichisdetailedintheFRACTIONAL  
DIVIDERsection. NotethattheVCOhasafrequencyrangeof10MHzto1200MHz. To maintainlowjitter,itisbesttomaximizetheVCOfrequency. Forexample,  
if thereferenceclockis100MHzanda200MHzclockisrequired,toachievethebestjitterperformance,multiplythe100MHzby12togettheVCOrunningat  
thehighestpossiblefrequencyof1200MHzandthendivideitdowntoget200MHz. Orifthereferenceclockis25MHzand20MHzistherequiredclock,multiply  
the25MHzby40togettheVCOrunningat1000MHzandthendivideitdowntoget20MHz. IfNissetto'0x00', theVCOwillslewtotheminimumfrequency.  
Post-Divider  
Q[9:0] are the bits used to program the 10-bit post-dividers on output banks OUT2-6. OUT1 bank does not have a 10-bit post-divider or any other post-  
divide along its path. The 10-bit post-dividers will divide down the output banks' frequency with integer values ranging from 1 to 1023.  
There is the option to choose between disabling the post-divider, utilizing a div/1, a div/2, or the 10-bit post-divider by using the PM[1:0] bits. Each bank,  
exceptforOUT1,hasasetofPMbits. Whendisablingthepost-divider,noclockwillappearattheoutputs,butwillremainpoweredon. Thevaluesarelisted  
inthetablebelow.  
P
00  
01  
PM[1:0]  
P Post-Divider  
disabled  
To Outputs  
VCO  
00  
01  
10  
11  
/2  
10  
11  
/2  
div/1  
/ (Q+2)  
div/2  
Q[9:0] + 2 (Eq. 6)  
PM[1:0]  
Post-Divider Diagram  
7
1...45678910...39

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