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5V9885TNLGI8 PDF预览

5V9885TNLGI8

更新时间： 2024-01-28 13:05:49
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路PC可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
39页 513K
描述
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

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5V9885TNLGI8 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：VFQFPN
包装说明：QCCN, LCC28,.24SQ,25针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.29
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/730035.2.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=730035
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=7300353D View：https://componentsearchengine.com/viewer/3D.php?partID=730035
Samacsys PartID：730035Samacsys Image：https://componentsearchengine.com/Images/9/5V9885TNLGI8.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/2/5V9885TNLGI8.jpgSamacsys Pin Count：29
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Quad Flat No-Lead
Samacsys Footprint Name：nlg28Samacsys Released Date：2020-01-16 10:43:20
Is Samacsys：NJESD-30 代码：S-XQCC-N28
JESD-609代码：e3长度：6.3 mm
湿度敏感等级：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：500 MHz封装主体材料：UNSPECIFIED
封装代码：QCCN封装等效代码：LCC28,.24SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：400 MHz认证状态：Not Qualified
子类别：Clock Generators最大压摆率：110 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：NO LEAD
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.3 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

5V9885TNLGI8 数据手册

 浏览型号5V9885TNLGI8的Datasheet PDF文件第7页浏览型号5V9885TNLGI8的Datasheet PDF文件第8页浏览型号5V9885TNLGI8的Datasheet PDF文件第9页浏览型号5V9885TNLGI8的Datasheet PDF文件第11页浏览型号5V9885TNLGI8的Datasheet PDF文件第12页浏览型号5V9885TNLGI8的Datasheet PDF文件第13页 
IDT5V9885T  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
Example  
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center spread of ±2%. Find the necessary spread spectrum register settings.  
Sincethespreadiscenter,theSS_OFFSETcanbesetto'0'. SolveforthenominalMvalue;keepinmindthatthenominalMshouldbechosentomaximize  
the VCO. Start with D = 1, using Eq.10 and Eq.11.  
MNOM = 1200MHz / 25MHz = 48  
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we have the nominal M value, we can determine TSSC and NSSC by using Eq.12.  
Nssc * Tssc = 25MHz / (33KHz * 4) = 190  
However, using Eq. 7 and Eq.8, we find that the closest value is when TSSC = 14 and NSSC = 6. Keep in mind to maximize the number of samples used  
toenhancetheprofileofthespreadspectrumwaveform.  
Tssc = 14 + 2 = 16  
Nssc = 6 * 2 = 12  
Nssc * Tssc = 192  
UseEq.14todeterminethevalueofthesigma-delta-encodedsamples.  
±2% = Σ∆ * 100  
64 * 48  
Σ∆ = 61.44  
Eitherroundupordowntothenearestintegervalue. Therefore,weendupwith61or62forsigma-delta-encodedsamples. Sincethesigma-delta-encoded  
samplesmustnotexceed63with SS_OFFSETsetto'0', 61or62iswellwithinthelimits. Itisthediscretionoftheusertodefinetheshapeof theprofilethat  
isbettersuitedfortheintendedapplication.  
Using Eq.14 again, the actual spread for the sigma-delta-encoded samples of 61 and 62 are ±1.99% and ±2.02%, respectively.  
UseEq.10todetermineiftheX2bitneedstobeset;  
Amplitude = 48 * (1.99 or 2.02) / 100 = 0.48 < 1  
2
Therefore, the X2 = '0 '. The dither bit is left to the discretion of the user.  
The example above was of a center spread using spread spectrum. For down spread, the nominal M value can be set one integer value lower to 43.  
Note that the 5V9885T should not be programmed with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator.  
ThePLLloopbandwidthmustbeatleast10xthemodulationfrequencyalongwithhigherdamping(largerωuz)topreventthespreadspectrumfrombeingfiltered  
andreduceextraneousnoise. RefertotheLOOPFILTERsectionformoredetailonωuz.TheA[3:0]mustbeusedforspreadspectrum,evenifthetotalmultiplier  
value is an even integer.  
FRACTIONALDIVIDER  
There is the option for the feedback-divider to be programmed as a fractional divider for only PLL0 and PLL. By setting TSSC > '0' and SD bits to '0', the  
SS_OFFSETbitswoulddeterminethefractionaldividevalue.SeetheSPREADSPECTRUMGENERATIONsectionformoredetailsontheTSSC,SD,and  
SS_OFFSET bits. The following equation governs how the fractional divide value is set.  
M = 2*N[11:0] + A[3:0] + 1 + SS_OFFSET[5:0] *1/64  
10  
1...78910111213...39

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