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5V9885TNLGI8

更新时间： 2024-01-23 20:45:35

品牌	Logo	应用领域
艾迪悌 - IDT		晶体时钟发生器微控制器和处理器外围集成电路 PC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
39页	513K
描述
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

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技术参数
数据手册

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5V9885TNLGI8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	VFQFPN
包装说明：	QCCN, LCC28,.24SQ,25	针数：	28
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.29
Samacsys Confidence：	3	Samacsys Status：	Released
2D Presentation：	https://componentsearchengine.com/2D/0T/730035.2.1.png	Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=730035
PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=730035	3D View：	https://componentsearchengine.com/viewer/3D.php?partID=730035
Samacsys PartID：	730035	Samacsys Image：	https://componentsearchengine.com/Images/9/5V9885TNLGI8.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/2/5V9885TNLGI8.jpg	Samacsys Pin Count：	29
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Quad Flat No-Lead
Samacsys Footprint Name：	nlg28	Samacsys Released Date：	2020-01-16 10:43:20
Is Samacsys：	N	JESD-30 代码：	S-XQCC-N28
JESD-609代码：	e3	长度：	6.3 mm
湿度敏感等级：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出时钟频率：	500 MHz	封装主体材料：	UNSPECIFIED
封装代码：	QCCN	封装等效代码：	LCC28,.24SQ,25
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	电源：	3.3 V
主时钟/晶体标称频率：	400 MHz	认证状态：	Not Qualified
子类别：	Clock Generators	最大压摆率：	110 mA
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	NO LEAD
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	6.3 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

5V9885TNLGI8 数据手册

IDT5V9885T

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

INDUSTRIALTEMPERATURERANGE

Spread Spectrum

Pre-Divider (D) Values

Multiplier (M) Values

Programmable Loop Bandwidth

GenerationCapability

PLL0

PLL1

PLL2

1 - 255

2 - 8190

1 - 4095

yes

REFERENCE CLOCK INPUT PINS AND

SELECTION

XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)

Parameter

Bits

Step

Min

Max

Units

The 5V9885T supports up to two clock inputs. One of the clock inputs

(XTALIN/ REFIN) can be driven by either an external crystal or a reference

clock. The second clock input (CLKIN) can only be driven from an external

referenceclock.Eitherclockinputcanbesetasatheprimaryclock. Theprimary

clockdesignation istoestablishwhichisthemainreferenceclocktothePLLs.

Thenon-primaryclockisdesignatedasthesecondaryclockincasetheprimary

clock goes absent and a backup is needed. The PRIMCLK bit (0x34)

determineswhichclockinputwillbetheprimaryclock. WhenPRIMCLKbitis

"0",itwillselectXTALIN/REFINastheprimary,andwhen"1",itwillselectCLKIN

astheprimary. Thetwoexternalreferenceclockscanbemanuallyselected

using the GIN5/CLK_SEL pin, except in Manual Frequency Control (MFC)

mode2,orviaprogrammingbyhardwiringtheCLK_SELpinandtogglingthe

PRIMCLKbit. FormoredetailsontheMFCmodes,refertotheCONFIGURING

MULTI-PURPOSEI/Ossection. WhenCLK_SELisLOW,theprimaryclock

isselectedandwhenHIGH,thesecondaryclockisselected. TheSMbits(0x34)

mustbesetto"0x"formanualswitchoverwhichisdetailedinSWITCHOVER

MODESsection.

XTALCAP

0.125

When using an external reference clock instead of a crystal on the XTAL/

REFINpin,theinputloadcapacitorsmaybecompletelybypassed.Thisallows

fortheinputfrequencytobeupto200MHz. Whenusinganexternalreference

clock,theXTALOUTpinmustbeleftfloating,XTALCAPmustbeprogrammed

to the default value of "0", and crystal drive strength bit, XDRV (0x06), must

be set to the default value of "11".

CLKIN Pin

CLKIN pin is a regular clock input pin, and can be driven up to 400MHz.

PRE-SCALER,FEEDBACK-DIVIDER,AND

POST-DIVIDER

Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider

whichallowstheusertogeneratethreeuniquenon-integer-relatedfrequencies.

For output banks OUT2-OUT6, each bank has a 10-bit post-divider. The

following equation governs how the frequency on output banks OUT2-6 is

calculated.

GIN5/CLK_SEL

Selected Clock Input

Primary

Secondary

(^M)

Crystal Input (XTALIN/REFIN)

FOUT = FIN * D

(Eq. 2)

Thecrystaloscillatorsshouldbefundamentalmodequartzcrystals:overtone

crystals are not suitable. Crystal frequency should be specified for parallel

resonancewith50Ωmaximumequivalentseriesresonance.

P * 2

WhereFIN isthereferencefrequency,Misthetotalfeedback-dividervalue,

Disthepre-scalervalue,Pisthetotalpost-dividervalue,andFOUT istheresulting

output bank frequency. The value 2 in the denominator is due to the divide-

by-2oneachoftheoutputbanksOUT2-6. NotethatOUT1doesnothaveany

typeofpost-divider. Also,programminganyofthedividersmaycauseglitches

ontheoutputs.

WhentheXTALIN/REFINpinisdrivenbyacrystal,itisimportanttosetthe

internal oscillator inverter drive strength and internal tuning/load capacitor

values correctly to achieve the best clock performance. These values are

programmable through either I²C or JTAG interface to allow for maximum

compatibilitywithcrystalsfromvariousmanufacturers,processes,performances,

andqualities.Theinternalloadcapacitorsaretrueparallel-platecapacitorsfor

ultra-linearperformance. Parallel-platecapacitorswerechosentoreducethe

frequencyshiftthatoccurswhennon-linearloadcapacitanceinteractswithload,

bias, supply, and temperature changes. External non-linear crystal load

capacitors should not be used for applications that are sensitive to absolute

frequencyrequirements.Thevalueoftheinternalloadcapacitorsaredetermined

byXTALCAP[7:0]bits,(0x07).Theloadcapacitancecanbesetwitharesolution

of0.125pFforatotalcrystalloadrangeof3.5pFto35.5pF. Thisvalueshould

be set to two times the crystal load capacitance value stated by the vendor,

subtractingoutboardcapacitancevalue.Checkwiththevendor'scrystalload

capacitancespecificationfortheexactsettingtotunetheinternalloadcapacitor.

Thefollowingequationgovernshowthetotalinternalloadcapacitanceisset.

Ex.: For crystal capacitance = 12pF

Pre-Scaler

D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for

PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the

referenceclockwithintegervaluesrangingfrom1to255. Tomaintainlowjitter,

thedivideddownclockmustbehigherthan400KHz;itisbesttousethesmallest

Ddividervaluepossible. IfDissetto'0x00',thenthiswillpowerdownthePLL

andalltheoutputsassociatedwiththatPLL.

For board capacitance = 3pF each leg

XTALCAP = 2x [12-3] = 18pF

1...3 4 567 8 9...39

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