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5P35021 PDF预览

5P35021

更新时间: 2024-10-28 01:15:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
34页 453K
描述
VersaClock Programmable Clock Generator

5P35021 数据手册

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VersaClock® Programmable Clock Generator  
5P35021  
DATASHEET  
Description  
Features  
The 5P35021 is the latest VersaClock programmable clock  
generator and is designed for low-power, consumer, and  
high-performance PCI Express applications. The 5P35021  
device is a 3 PLLs architecture design; each PLL is  
individually programmable and allows up to 3 unique  
frequency outputs.  
Configurable OE pin function as OE, PD#, PPS or DFC  
control function  
Configurable PLL bandwidth/minimizes jitter peaking  
PPS: Proactive Power Saving features save power during  
the end device power down mode  
PPB: Performance- Power Balancing feature allow user to  
minimum power consumption base on required  
performance  
The 5P35021 has built-in unique features such as Proactive  
Power Saving (PPS), Performance-Power Balancing (PPB),  
Overshot Reduction Technology (ORT) and extreme low  
power DCO. An internal OTP memory allows the user to store  
the configuration in the device. After power up, the user can  
DFC: Dynamic Frequency Control feature allows user to  
program up to 4 difference frequencies and switch  
dynamically  
2
Spread spectrum clock support to lower system EMI  
Store user configuration into OTP memory  
change the device register settings through the I C interface  
2
when I C mode is selected. It also has programmable VCO  
2
and PLL source selection to allow the user to do  
power-performance optimization based on the application  
requirements.  
I C interface  
Key Specifications  
PCIe clocks phase jitter: PCIe Gen3  
Differential clocks < 3 ps rms jitter integer range 12kHz–  
20MHz  
The device provides one single-ended output and two pairs of  
differential outputs that support LVCMOS, LVPECL, LVDS and  
LPHCSL. The low power 32.768kHz clock is supported with  
only less than 2µA current consumption for system RTC  
reference clock.  
< 2µA DCO to generate 32.768kHz clock  
Output Features  
2 DIFF outputs with configurable LPHSCL, LVDS, LVPECL,  
LVCMOS output pairs. 1MHz–500MHz (160MHz/ with  
LVCMOS mode)  
Typical Applications  
PCIe Gen1/2/3 clock generator  
Consumer application crystal replacements  
SmartDevice, Handheld, Computing and Consumer  
applications  
1 LVCMOS output: 1MHz–160MHz  
Maximum 5 LVCMOS outputs as 1 × SE + 2 × DIFF_T/C as  
LVCMOS  
Low Power 32.768kHz clock supported on SE1  
Pin Assignment  
19  
18  
17  
20  
16  
1
15  
14  
13  
12  
11  
DIFF1  
DIFF1B  
VDDDIFF1  
OE1  
VDDA  
2
SDA_DFCO  
3
5P35021  
SEL_DFC/SCL_DFC1  
4
CLKIN/X2  
5
SE1  
CLKINB/X1  
6
7
8
9
10  
5P35021 NOVEMBER 30, 2017  
1
©2017 Integrated Device Technology, Inc.  

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